M38039FFHFP#U0 Renesas Electronics America, M38039FFHFP#U0 Datasheet - Page 14

• Manufacturer Part Number: M38039FFHFP#U0
• Description: IC 740 MCU FLASH 60K 64QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039FFHFP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H)
Rev.3.11
REJ03B0017-0311
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an
arithmetic operation and 3 flags which decide MCU operation.
Branch operations can be performed by testing the Carry (C)
flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.
In decimal mode, the Z, V, N flags are not valid.
Bit 0: Carry flag (C)
Bit 1: Zero flag (Z)
Bit 2: Interrupt disable flag (I)
Bit 3: Decimal mode flag (D)
Table 8
Set instruction
Clear instruction
The C flag contains a carry or borrow generated by the
arithmetic logic unit (ALU) immediately after an arithmetic
operation. It can also be changed by a shift or rotate
instruction.
The Z flag is set if the result of an immediate arithmetic
operation or a data transfer is “0”, and cleared if the result is
anything other than “0”.
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it
is “1”.
Decimal correction is automatic in decimal mode. Only the
ADC and SBC instructions can execute decimal arithmetic.
Set and clear instructions of each bit of processor status register
Apr 5, 2006
C flag
SEC
CLC
Page 12 of 113
Z flag
−
−
I flag
SEI
CLI
D flag
SED
CLD
Bit 4: Break flag (B)
Bit 5: Index X mode flag (T)
Bit 6: Overflow flag (V)
Bit 7: Negative flag (N)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the
processor status register is always “0”. When the BRK
instruction is used to generate an interrupt, the processor
status register is pushed onto the stack with the break flag set
to “1”.
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”,
direct arithmetic operations and direct data transfers are
enabled between memory locations.
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds +127 to −
128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instruction is stored
in the overflow flag.
The N flag is set if the result of an arithmetic operation or
data transfer is negative. When the BIT instruction is
executed, bit 7 of the memory location operated on by the
BIT instruction is stored in the negative flag.
B flag
−
−
T flag
SET
CLT
V flag
CLV
−
N flag
−
−