M38039FFHFP#U0 Renesas Electronics America, M38039FFHFP#U0 Datasheet - Page 31

• Manufacturer Part Number: M38039FFHFP#U0
• Description: IC 740 MCU FLASH 60K 64QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039FFHFP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H)
Rev.3.11
REJ03B0017-0311
TIMERS
• 8-bit Timers
The 3803 group (Spec.H) has four 8-bit timers: timer 1, timer 2,
timer X, and timer Y.
The timer 1 and timer 2 use one prescaler in common, and the
timer X and timer Y use each prescaler. Those are 8-bit
prescalers. Each of the timers and prescalers has a timer latch or
a prescaler latch.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down-counters. When the timer reaches “00
underflow occurs at the next count pulse and the contents of the
corresponding timer latch are reloaded into the timer and the
count is continued. When the timer underflows, the interrupt
request bit corresponding to that timer is set to “1”.
• Timer divider
The divider count source is switched by the main clock division
ratio selection bits of CPU mode register (bits 7 and 6 at address
003B
(middle-speed mode), X
(low-speed mode), X
• Prescaler 12
The prescaler 12 counts the output of the timer divider. The count
source is selected by the timer 12, X count source selection
register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512, 1/1024 of f(X
• Timer 1 and Timer 2
The timer 1 and timer 2 counts the output of prescaler 12 and
periodically set the interrupt request bit.
• Prescaler X and prescaler Y
The prescaler X and prescaler Y count the output of the timer
divider or f(X
X count source selection register (address 000E
Y, Z count source selection register (address 000F
1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of
f(X
IN
) or f(X
16
). When these bits are “00” (high-speed mode) or “01”
CIN
CIN
Apr 5, 2006
); and f(X
). The count source is selected by the timer 12,
IN
CIN
) or f(X
IN
is selected.
CIN
is selected. When these bits are “10”
).
CIN
).
Page 29 of 113
16
) and the timer
16
) among 1/2,
16
”, an
• Timer X and Timer Y
The timer X and timer Y can each select one of four operating
modes by setting the timer XY mode register (address 0023
(1) Timer mode
• Mode selection
This mode can be selected by setting “00” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the timer XY mode register (address
0023
• Explanation of operation
The timer count operation is started by setting “0” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 0023
When the timer reaches “00
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
(2) Pulse Output Mode
• Mode selection
This mode can be selected by setting “01” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the timer XY mode register (address
0023
• Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR
not the output of CNTR
specified by their active edge switch bits when writing to the
timer. When the CNTR
CNTR
register (address 0023
When it is “1”, the output starts with “L” level.
Switching the CNTR
reverse the output level of the corresponding CNTR
pin.
• Precautions
Set the double-function port of CNTR
P5
(3) Event Counter Mode
• Mode selection
This mode can be selected by setting “10” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the timer XY mode register (address
0023
• Explanation of operation
The operation is the same as the timer mode’s except that the
timer counts signals input from the CNTR
valid edge for the count operation depends on the CNTR
edge switch bit (bit 2) or the CNTR
of the timer XY mode register (address 0023
the rising edge is valid. When it is “1”, the falling edge is valid.
• Precautions
Set the double-function port of CNTR
P5
4
4
/P5
/P5
16
16
16
).
).
).
1
5
5
to output in this mode.
to input in this mode.
active edge switch bit (bit 6) of the timer XY mode
0
/CNTR
1
16
0
pin. Regardless of the timer counting or
0
) is “0”, the output starts with “H” level.
0
or CNTR
/CNTR
active edge switch bit (bit 2) and the
16
”, an underflow occurs at the next
1
pin is initialized to the level of
1
1
active edge switch bit will
active edge switch bit (bit 6)
16
).
0
0
/CNTR
/CNTR
0
or CNTR
16
). When it is “0”,
1
1
pin and port
pin and port
0
or CNTR
1
pin. The
0
active
16
).
1