M38039FFHFP#U0 Renesas Electronics America, M38039FFHFP#U0 Datasheet - Page 36

• Manufacturer Part Number: M38039FFHFP#U0
• Description: IC 740 MCU FLASH 60K 64QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039FFHFP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H)
Rev.3.11
REJ03B0017-0311
• 16-bit Timer
The timer Z is a 16-bit timer. When the timer reaches “0000
a n u n d e r f l o w o c c u r s a t t h e n e x t c o u n t p u l s e a n d t h e
corresponding timer latch is reloaded into the timer and the count
is continued. When the timer underflows, the interrupt request bit
corresponding to the timer Z is set to “1”.
When reading/writing to the timer Z, perform reading/writing to
both the high-order byte and the low-order byte. When reading
the timer Z, read from the high-order byte first, followed by the
low-order byte. Do not perform the writing to the timer Z
between read operation of the high-order byte and read operation
of the low-order byte. When writing to the timer Z, write to the
low-order byte first, followed by the high-order byte. Do not
perform the reading to the timer Z between write operation of the
low-order byte and write operation of the high-order byte.
The timer Z can select the count source by the timer Z count
source selection bits of timer Y, Z count source selection register
(bits 7 to 4 at address 000F
Timer Z can select one of seven operating modes by setting the
timer Z mode register (address 002A
(1) Timer mode
• Mode selection
This mode can be selected by setting “000” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A
• Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(X
selected as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(X
count source.
• Interrupt
When an underflow occurs, the INT
(bit 0) of the interrupt request register 1 (address 003C
“1”.
• Explanation of operation
During timer stop, usually write data to a latch and a timer at the
same time to set the timer value.
The timer count operation is started by setting “0” to the timer Z
count stop bit (bit 6) of the timer Z mode register (address
002A
When the timer reaches “0000
next count pulse and the contents of timer latch are reloaded into
the timer and the count is continued.
When writing data to the timer during operation, the data is
written only into the latch. Then the new latch value is reloaded
into the timer at the next underflow.
16
).
Apr 5, 2006
16
CIN
).
16
); or f(X
).
16
Page 34 of 113
”, an underflow occurs at the
0
/timer Z interrupt request bit
16
CIN
).
) can be selected as the
IN
); or f(X
CIN
16
) is set to
) can be
16
”,
(2) Event counter mode
• Mode selection
This mode can be selected by setting “000” to the timer Z
operating mode bits (bits 2 to 0) and setting “1” to the
timer/event counter mode switch bit (bit 7) of the timer Z mode
register (address 002A
The valid edge for the count operation depends on the CNTR
active edge switch bit (bit 5) of the timer Z mode register
(address 002A
it is “1”, the falling edge is valid.
• Interrupt
The interrupt at an underflow is the same as the timer mode’s.
• Explanation of operation
The operation is the same as the timer mode’s.
Set the double-function port of CNTR
in this mode.
Figure.27 shows the timing chart of the timer/event counter
mode.
(3) Pulse output mode
• Mode selection
This mode can be selected by setting “001” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A
• Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(X
selected as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(X
count source.
• Interrupt
The interrupt at an underflow is the same as the timer mode’s.
• Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR
of the timer Z mode register (address 002A
starts with “H” level. When it is “1”, the output starts with “L”
level.
• Precautions
The double-function port of CNTR
automatically set to the timer pulse output port in this mode.
The output from CNTR
on CNTR
When the value of the CNTR
the output level of CNTR
Figure.28 shows the timing chart of the pulse output mode.
2
active edge switch bit by writing to the timer.
2
pin. When the CNTR
16
). When it is “0”, the rising edge is valid. When
16
16
2
CIN
).
).
pin is initialized to the level depending
2
pin is inverted.
); or f(X
2
active edge switch bit is changed,
2
active edge switch bit (bit 5)
CIN
2
pin and port P4
) can be selected as the
IN
2
pin and port P4
); or f(X
16
) is “0”, the output
CIN
7
) can be
to input
7
is
2