M38039FFHFP#U0 Renesas Electronics America, M38039FFHFP#U0 Datasheet - Page 112

• Manufacturer Part Number: M38039FFHFP#U0
• Description: IC 740 MCU FLASH 60K 64QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039FFHFP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H)
Rev.3.11
REJ03B0017-0311
Notes on Serial Interface
1. Notes when selecting clock synchronous serial I/O
(1) Stop of transmission operation
As for serial I/Oi (i = 1, 3) that can be used as either a clock
synchronous or an asynchronous (UART) serial I/O, clear the
serial I/Oi enable bit and the transmit enable bit to “0” (serial
I/Oi and transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/Oi enable bit is cleared to
“0” (serial I/Oi disabled), the internal transmission is running (in
this case, since pins TxDi, RxDi, S
I/O ports, the transmission data is not output). When data is
written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/Oi
enable bit is set to “1” at this time, the data during internally
shifting is output to the TxDi pin and an operation failure occurs.
(2) Stop of receive operation
As for serial I/Oi (i = 1, 3) that can be used as either a clock
synchronous or an asynchronous (UART) serial I/O, clear the
receive enable bit to “0” (receive disabled), or clear the serial
I/Oi enable bit to “0” (serial I/Oi disabled).
(3) Stop of transmit/receive operation
As for serial I/Oi (i = 1, 3) that can be used as either a clock
synchronous or an asynchronous (UART) serial I/O, clear both
the transmit enable bit and receive enable bit to “0” (transmit and
receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception
cannot be stopped.)
<Reason>
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception. If any one of transmission and
reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also
operates for data reception. Accordingly, the transmission circuit
does not stop by clearing only the transmit enable bit to “0”
(transmit disabled). Also, the transmission circuit is not
initialized by clearing the serial I/Oi enable bit to “0” (serial I/Oi
disabled) (refer to (1) in 1.).
2. Notes when selecting clock asynchronous serial I/O
(1) Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial I/Oi
enable bit (i = 1, 3) to “0”.
<Reason>
This is the same as (1) in 1.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial I/Oi
enable bit (i = 1, 3) to “0”.
<Reason>
This is the same as (1) in 1.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
Apr 5, 2006
Page 110 of 113
CLK
i, and S
RDY
i function as
3. S
When signals are output from the S
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the S
bit, and the transmit enable bit to “1” (transmit enabled).
4. Setting serial I/Oi (i = 1, 3) control register again
Set the serial I/Oi control register again after the transmission
and the reception circuits are reset by clearing both the transmit
enable bit and the receive enable bit to “0.”
Fig 90. Sequence of setting serial I/Oi (i = 1, 3) control
5. Data transmission control with referring to transmit
After the transmit data is written to the transmit buffer register,
the transmit shift register completion flag changes from “1” to
“0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after writing
the data to the transmit buffer register, note the delay.
6. Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the
S
transmit buffer register at “H” of the S
7. Transmit interrupt request when transmit enable bit
When using the transmit interrupt, take the following sequence.
(1) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to
(2) Set the tranasmit enable bit to “1”.
(3) Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to
(4) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to
<Reason>
When the transmission enable bit is set to “1”, the transmit buffer
empty flag and transmit shift register shift completion flag are
also set to “1”.
Therefore, regardless of selecting which timing for the
generating of transmit interrupts, the interrupt request is
generated and the transmit interrupt request bit is set at this point.
8. Writing to baud rate generator i (BRGi) (i = 1, 3)
Write data to the baud rate generator i (BRGi) (i = 1, 3) while the
transmission/reception operation is stopped.
CLK
shift register completion flag
is set
RDY
Clear both the transmit enable bit (TE) and
the receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of the serial I/Oi
control register
Set both the transmit enable bit (TE) and the
receive enable bit (RE), or one of them to “1”
“0” (disabled).
“0” after 1 or more instruction has executed.
“1” (enabled).
i (i = 1, 3) input level. Also, write the transmit data to the
i (i = 1, 3) output of reception side
register again
RDY
CLK
i pin on the reception side
i input level.
RDY
Can be set with the
LDM instruction at
the same time
i output enable