M38039FFHFP#U0 Renesas Electronics America, M38039FFHFP#U0 Datasheet - Page 27

• Manufacturer Part Number: M38039FFHFP#U0
• Description: IC 740 MCU FLASH 60K 64QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039FFHFP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H)
Rev.3.11
REJ03B0017-0311
INTERRUPTS
The 3803 group (Spec.H)’s interrupts are a type of vector and
occur by 16 sources among 21 sources: eight external, twelve
internal, and one software.
• Interrupt Control
Each interrupt is controlled by an interrupt request bit, an
interrupt enable bit, and the interrupt disable flag except for the
software interrupt set by the BRK instruction. An interrupt
occurs if the corresponding interrupt request and enable bits are
“1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The reset and the BRK instruction cannot be disabled with any
flag or bit. The I (interrupt disable) flag disables all interrupts
except the reset and the BRK instruction interrupt.
When several interrupt requests occur at the same time, the
interrupts are received according to priority.
• Interrupt Operation
By acceptance of an interrupt, the following operations are
automatically performed:
• Interrupt Source Selection
Which of each combination of the following interrupt sources
can be selected by the interrupt source selection register (address
0039
• External Interrupt Pin Selection
The occurrence sources of the external interrupt INT
can be selected from either input from INT
input from INT
switch bit of interrupt edge selection register (bit 6 of address
003A
1. The contents of the program counter and the processor sta-
2. The interrupt disable flag is set and the corresponding inter-
3. The interrupt jump destination address is read from the vec-
1. INT
2. CNTR
3. Serial I/O2 or Timer Z
4. INT
5. A/D converter or serial I/O3 transmission
16
tus register are automatically pushed onto the stack.
rupt request bit is cleared.
tor table into the program counter.
16
).
).
4
0
or CNTR
or Timer Z
1
or Serial I/O3 reception
Apr 5, 2006
01
and INT
2
41
pin by the INT
Page 25 of 113
00
and INT
0
, INT
0
4
and INT
40
interrupt
pin, or
4
<Notes>
When setting the followings, the interrupt request bit may be set
to “1”.
When not requiring for the interrupt occurrence synchronized
with these setting, take the following sequence.
(1) Set the corresponding interrupt enable bit to “0” (disabled).
(2) Set the interrupt edge select bit (the active edge switch bit)
(3) Set the corresponding interrupt request bit to “0” after 1 or
(4) Set the corresponding interrupt enable bit to “1” (enabled).
• When setting external interrupt active edge
• When switching interrupt sources of an interrupt vector
or the interrupt source select bit.
more instructions have been executed.
Related register: Interrupt edge selection register
address where two or more interrupt sources are allocated
Related register: Interrupt source selection register
(address 003A
Timer XY mode register (address 0023
Timer Z mode register (address 002A
(address 0039
16
16
)
)
16
16
)
)