HD6413003TF16 Renesas Electronics America, HD6413003TF16 Datasheet - Page 15

• Manufacturer Part Number: HD6413003TF16
• Description: IC H8 MCU ROMLESS QFP112
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

13.3
13.4
13.5
Section 14
14.1
14.2
14.3
14.4
14.5
14.6
Section 15
15.1
15.2
15.3
Section 16
16.1
16.2
13.2.8
Operation ........................................................................................................................ 450
13.3.1
13.3.2
13.3.3
13.3.4
SCI Interrupts.................................................................................................................. 477
Usage Notes .................................................................................................................... 478
Overview ........................................................................................................................ 483
14.1.1
14.1.2
14.1.3
14.1.4
Register Descriptions...................................................................................................... 487
14.2.1
14.2.2
14.2.3
CPU Interface ................................................................................................................. 492
Operation ........................................................................................................................ 493
14.4.1
14.4.2
14.4.3
14.4.4
Interrupts ........................................................................................................................ 499
Usage Notes .................................................................................................................... 499
Overview ........................................................................................................................ 501
15.1.1
15.1.2
System Control Register (SYSCR)................................................................................. 503
Operation ........................................................................................................................ 504
Overview ........................................................................................................................ 505
16.1.1
Oscillator Circuit ............................................................................................................ 506
16.2.1
16.2.2
Bit Rate Register (BRR) ................................................................................. 441
Overview......................................................................................................... 450
Operation in Asynchronous Mode.................................................................. 452
Multiprocessor Communication ..................................................................... 461
Synchronous Operation .................................................................................. 468
A/D Converter
Features........................................................................................................... 483
Block Diagram................................................................................................ 484
Input Pins ........................................................................................................ 485
Register Configuration.................................................................................... 486
A/D Data Registers A to D (ADDRA to ADDRD) ........................................ 487
A/D Control/Status Register (ADCSR) .......................................................... 488
A/D Control Register (ADCR) ....................................................................... 491
Single Mode (SCAN = 0) ............................................................................... 493
Scan Mode (SCAN = 1).................................................................................. 495
Input Sampling and A/D Conversion Time .................................................... 497
External Trigger Input Timing........................................................................ 498
RAM
Block Diagram................................................................................................ 501
Register Configuration.................................................................................... 502
Clock Pulse Generator
Block Diagram................................................................................................ 505
Connecting a Crystal Resonator ..................................................................... 506
External Clock Input....................................................................................... 508
............................................................................................................. 501
............................................................................................ 483
............................................................................. 505