HD6413003TF16 Renesas Electronics America, HD6413003TF16 Datasheet - Page 507

• Manufacturer Part Number: HD6413003TF16
• Description: IC H8 MCU ROMLESS QFP112
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

14.2 Register Descriptions
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the
upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an
A/D data register are reserved bits that always read 0. Table 14-3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 14.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 14-3 Analog Input Channels and A/D Data Registers
Group 0
AN
AN
AN
AN
Bit
ADDRn
Initial value
Read/Write
(n = A to D)
Analog Input Channel
0
1
2
3
AD9
Group 1
AN
AN
AN
AN
15
R
0
4
5
6
7
AD8
14
R
0
AD7
13
R
0
A/D conversion data
10-bit data giving an
A/D conversion result
AD6
12
R
0
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
AD5
11
R
0
AD4
10
R
0
AD3
487
R
9
0
AD2
R
8
0
AD1
R
7
0
AD0
R
6
0
—
R
5
0
—
R
4
0
Reserved bits
—
R
3
0
—
R
2
0
—
R
1
0
—
R
0
0