HD6413003TF16 Renesas Electronics America, HD6413003TF16 Datasheet - Page 243

• Manufacturer Part Number: HD6413003TF16
• Description: IC H8 MCU ROMLESS QFP112
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 8-19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst
mode, and a transfer request for channel 0A is received while channel 1 is active.
Multiple-Channel Operation in Different Groups: If transfers are requested on channels in
groups 0 and 1 simultaneously, or if a transfer in one group is requested during a transfer in the
other group, the DMAC operates as follows.
•
•
•
•
ø
A
RD
HWR
23
When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it
activates the highest-priority channel at that time. If there are transfer requests for both
DMAC groups 0 and 1, a channel in group 0 is activated.
Once a transfer starts on a channel in one group, requests to other channels are held pending
until that channel releases the bus.
After each transfer in short address mode, and each externally-requested or cycle-steal
transfer in normal mode, the DMAC releases the bus and returns to step 1. If there is a
transfer request for a channel in the other group, that channel is activated immediately.
After completion of a burst-mode transfer, or after transfer of one block in block transfer
mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a
group-0 channel while a group-1 channel is active, however, the group-1 channel releases the
bus after completing the transfer of the current byte or word. When the bus is released, if
there is a transfer request for a channel in the other group, the DMAC is activated
immediately.
to A
,
LWR
0
Figure 8-19 Timing of Multiple-Channel Operations in the Same Group
DMAC cycle
(channel 1)
T
1
T
2
T
1
CPU
cycle
T
2
T
d
T
1
DMAC cycle
(channel 0A)
223
T
2
T
1
T
2
T
1
CPU
cycle
T
2
T
d
T
1
DMAC cycle
(channel 1)
T
2
T
1
T
2