HD6413003TF16 Renesas Electronics America, HD6413003TF16 Datasheet - Page 420

IC H8 MCU ROMLESS QFP112

HD6413003TF16

Manufacturer Part Number
HD6413003TF16
Description
IC H8 MCU ROMLESS QFP112
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413003TF16

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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11.3.3 Normal TPC Output
Sample Setup Procedure for Normal TPC Output: Figure 11-4 shows a sample procedure for
setting up normal TPC output.
ITU setup
Port and
TPC setup
ITU setup
Figure 11-4 Setup Procedure for Normal TPC Output (Example)
Select counting operation
Set next TPC output data
Set next TPC output data
Select TPC output trigger
Select interrupt request
Set initial output data
Select GR functions
Normal TPC output
Enable TPC output
Select port output
Compare match?
Set GRA value
Start counter
Yes
No
1
2
3
4
5
6
7
8
9
10
11
400
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Set TIOR to make GRA an output compare
register (with output inhibited).
Set the TPC output trigger period.
Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
Enable the IMFA interrupt in TIER.
The DMAC can also be set up to transfer
data to the next data register.
Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
Set the DDR bits of the input/output port
pins to be used for TPC output to 1.
Set the NDER bits of the pins to be used for
TPC output to 1.
Select the ITU compare match event to be
used as the TPC output trigger in TPCR.
Set the next TPC output values in the NDR bits.
Set the STR bit to 1 in TSTR to start the
timer counter.
At each IMFA interrupt, set the next output
values in the NDR bits.

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