HD6413003TF16 Renesas Electronics America, HD6413003TF16 Datasheet - Page 242

• Manufacturer Part Number: HD6413003TF16
• Description: IC H8 MCU ROMLESS QFP112
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.4.9 Multiple-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1 > channel 2 > channel 3, and
channel A > channel B. Table 8-12 shows the complete priority order. Group 0 and group 1
operate as two independent bus masters.
Table 8-12 Channel Priority Order
Bus Master
Group 0
Group 1
Multiple-Channel Operation in the Same Group: If transfers are requested on two or more
channels simultaneously in the same group, or if a transfer on one channel is requested during a
transfer on another channel in the same group, the DMAC operates as follows.
•
•
•
•
When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it
starts a transfer on the highest-priority channel at that time.
Once a transfer starts on one channel, requests to other channels in the same group are held
pending until that channel releases the bus.
After each transfer in short address mode, and each externally-requested or cycle-steal
transfer in normal mode, the DMAC releases the bus and returns to step 1. After releasing the
bus, if there is a transfer request for another channel in the same group, the DMAC requests
the bus again.
After completion of a burst-mode transfer, or after transfer of one block in block transfer
mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a
higher-priority channel or a bus request from a higher-priority bus master, however, the
DMAC releases the bus after completing the transfer of the current byte or word. After
releasing the bus, if there is a transfer request for another channel in the same group, the
DMAC requests the bus again.
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
Channel 2A
Channel 2B
Channel 3A
Channel 3B
Full Address Mode
Channel 0
Channel 1
Channel 2
Channel 3
222
Priority
High
Low