HD6413003TF16 Renesas Electronics America, HD6413003TF16 Datasheet - Page 91

IC H8 MCU ROMLESS QFP112

HD6413003TF16

Manufacturer Part Number
HD6413003TF16
Description
IC H8 MCU ROMLESS QFP112
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413003TF16

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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4.4 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
4.5 Stack Status after Exception Handling
Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
CCR
SP
PC
Note: In modes 1 and 2 only 20 PC bits are valid; the upper 4 bits are ignored.
Figure 4-5 Stack after Completion of Exception Handling
71

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