UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 102

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

<R>
100
(5) Port mode register 2 (PM2) and port mode control register 2 (PMC2)
Cautions 3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.
Remark n = 0, 1
When using the P21/TO00/TI010/ANI1/INTP0 pin for timer output, clear PM21, the output latch of P21, and
PMC21 to 0.
When using the P20/TI000/TOH1/ANI0 and P21/TO00/TI010/ANI1/INTP0 pins as a timer input, set PM20 and
PM21 to 1, and clear PMC20 and PMC21 to 0.
At this time, the output latches of P20 and P21 can be either 0 or 1.
PM2 and PMC2 are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the value of PM2 to FFH, and clears the value of PMC2 to 00H.
Note
Address: FF22H After reset: FFH R/W
Symbol
PM2
PD78F921x only
4. The sampling clock used to eliminate noise differs when the valid edge of TI000 is used
5. When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer
as the count clock and when it is used as a capture trigger. In the former case, the count
clock is f
00 (PRM00). The capture operation is not performed until the valid edge is sampled and
the valid level is detected twice, thus eliminating noise with a short pulse width.
output pin (TO00). When using P21 as the timer output pin (TO00), it cannot be used as
the input pin (TI010) of the valid edge.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the
<2> If the TM00 operation is stopped while the TI0n0 pin is at high level, TM00 operation
<3> If the TM00 operation is stopped while the TI0n0 pin is at low level, TM00 operation
PM2n
7
1
0
1
operation of 16-bit timer counter 00 (TM00) is enabled
is then enabled after a low level is input to the TI0n0 pin
is then enabled after a high level is input to the TI0n0 pin
If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
If the falling edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is
enabled.
If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
XP
Figure 6-9. Format of Port Mode Register 2 (PM2)
Output mode (output buffer on)
Input mode (output buffer off)
, and in the latter case the count clock is selected by prescaler mode register
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6
1
User’s Manual U16994EJ6V0UD
5
1
P2n pin I/O mode selection (n = 0 to 3)
4
1
PM23
3
Note
PM22
2
PM21
1
PM20
0