UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 212

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

14.3 Registers Controlling Low-Voltage Detector
(1) Low-voltage detect register (LVIM)
210
The low-voltage detector is controlled by the following registers.
Address: FF50H
Symbol
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H
LVIM
Low-voltage detect register (LVIM)
Low-voltage detection level select register (LVIS)
Notes 1.
Cautions 1. To stop LVI, follow either of the procedures below.
LVION
LVIF
LVION
LVIMD
<7>
0
1
0
1
0
1
Note 4
2.
3.
4.
Note 3
After reset: 00H
2. Be sure to set bits 2 to 6 to 0.
For a reset by LVI, the value of LVIM is not initialized.
Bit 0 is a read-only bit.
When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is
confirmed at LVIF.
The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
Disable operation
Enable operation
Generate interrupt signal when supply voltage (V
Generate internal reset signal when supply voltage (V
Supply voltage (V
Supply voltage (V
Figure 14-2. Format of Low-Voltage Detect Register (LVIM)
When using 8-bit manipulation instruction: Write 00H to LVIM.
When using 1-bit memory manipulation instruction: Clear LVION to 0.
6
0
Note 1
CHAPTER 14 LOW-VOLTAGE DETECTOR
R/W
5
0
DD
DD
) ≥ detection voltage (V
) < detection voltage (V
Low-voltage detection operation mode selection
Note 2
User’s Manual U16994EJ6V0UD
Enabling low-voltage detection operation
4
0
Low-voltage detection flag
Note 1
.
LVI
LVI
3
0
), or when operation is disabled
)
DD
) < detection voltage (V
DD
) < detection voltage (V
2
0
LVIMD
<1>
LVI
)
LVI
LVIF
)
<0>