UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 346

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

344
Watchdog
timer
A/D
converter
(
21x only)
Function
μ
PD78F9
WDTM:
Watchdog timer
mode register
WDTE:
Watchdog timer
enable register
When “low-
speed internal
oscillator cannot
be stopped” is
selected by
option byte
when “low-
speed internal
oscillator can be
stopped by
software” is
selected by
option byte
Sampling time
and A/D
conversion time
Block diagram
ADM: A/D
converter mode
register
ADS: Analog
input channel
specification
register
ADCR: 10-bit
A/D conversion
result register
Details of
Function
WDTM cannot be set by a 1-bit memory manipulation instruction.
When using the flash memory programming by self programming, set the overflow
time for the watchdog timer so that enough overflow time is secured (Example 1-
byte writing: 200
If a value other than ACH is written to WDTE, an internal reset signal is
generated.
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
The value read from WDTE is 9AH (this differs from the written value (ACH)).
In this mode, operation of the watchdog timer cannot be stopped even during
STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the low-
speed internal oscillation clock can be selected as the count source, so clear the
watchdog timer using the interrupt request of TMH1 before the watchdog timer
overflows after STOP instruction execution. If this processing is not performed,
an internal reset signal is generated when the watchdog timer overflows after
STOP instruction execution.
In this mode, watchdog timer operation is stopped during HALT/STOP instruction
execution. After HALT/STOP mode is released, counting is started again using
the operation clock of the watchdog timer set before HALT/STOP instruction
execution by WDTM. At this time, the counter is not cleared to 0 but holds its
value.
The above sampling time and conversion time do not include the clock frequency
error. Select the sampling time and conversion time such that Notes 2 and 3
above are satisfied, while taking the clock frequency error into consideration (an
error margin maximum of ±5% when using the high-speed internal oscillator).
In
converter. Be sure to connect V
In
input. When using the A/D converter, stabilize V
(2.7 to 5.5 V).
The above sampling time and conversion time do not include the clock frequency
error. Select the conversion time taking the clock frequency error into
consideration (an error margin maximum of ±5% when using the high-speed
internal oscillator).
If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped
(ADCS = 0) and then A/D conversion is started, execute two NOP instructions or
an instruction equivalent to two machine cycles, and set ADCS to 1.
A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
Be sure to clear bits 6, 2, and 1 to 0.
Be sure to clear bits 2 to 7 of ADS to 0.
When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read
the conversion result following conversion completion before writing to ADM and
ADS. Using timing other than the above may cause an incorrect conversion result
to be read.
μ
μ
PD78F921x, V
PD78F921x, V
APPENDIX D LIST OF CAUTIONS
User’s Manual U16994EJ6V0UD
μ
s MIN., 1-block deletion: 10 ms MIN.).
SS
DD
functions alternately as the ground potential of the A/D
functions alternately as the A/D converter reference voltage
SS
to a stabilized GND (= 0 V).
Cautions
DD
at the supply voltage used
p. 150
p. 150
p. 150
p. 150
p. 150
p. 151
p. 153
p. 158
p. 159
p. 159
p. 163
p. 163
p. 163
p. 163
p. 164
p. 164
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