UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 348

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

346
A/D
converter
(
21x only)
Interrupt
functions
Function
μ
PD78F9
Input
impedance of
ANI0 to ANI3
pins
Interrupt
request flag
(ADIF)
Conversion
results just after
A/D conversion
start
A/D conversion
result register
(ADCR,
ADCRH) read
operation
Operating
current at
conversion
waiting mode
IF0: Interrupt
request flag
registers,
MK0: Interrupt
mask flag
registers
INTM0: External
interrupt mode
register 0
Interrupt
requests are
held pending
Details of
Function
In this A/D converter, the internal sampling capacitor is charged and sampling is
performed during sampling time.
Since only the leakage current flows other than during sampling and the current
for charging the capacitor also flows during sampling, the input impedance
fluctuates during sampling and other statuses.
If the shortest conversion time of the reference voltage is used, to perform
sufficient sampling, it is recommended to make the output impedance of the
analog input source 1 kΩ or lower, or attach a capacitor of around 0.01
μ
When writing the flash memory on-board, supply a stabilized analog voltage to the
ANI2 and ANI3 pins, without attaching a capacitor. Because the communication
pulse may change and the communication may fail if a capacitor is attached to
remove noise.
The interrupt request flag (ADIF) is not cleared even if the analog input channel
specification register (ADS) is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D
conversion result and ADIF for the pre-change analog input may be set just
before the ADS rewrite. Caution is therefore required since, at this time, when
ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D
conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D
conversion operation is resumed.
The first A/D conversion value immediately after A/D conversion starts may not
fall within the rating range if the ADCS bit is set to 1 within 1
was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures
such as polling the A/D conversion end interrupt request (INTAD) and removing
the first conversion result.
When a write operation is performed to the A/D converter mode register (ADM)
and analog input channel specification register (ADS), the contents of ADCR and
ADCRH may become undefined. Read the conversion result following conversion
completion before writing to ADM and ADS. Using a timing other than the above
may cause an incorrect conversion result to be read.
The DC characteristic of the operating current during the STOP mode is not
satisfied due to the conversion waiting mode (only the comparator consumes
power), when bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register
(ADM) are set to 0 and 1 respectively.
Because P21 and P32 have an alternate function as external interrupt inputs,
when the output level is changed by specifying the output mode of the port
function, an interrupt request flag is set. Therefore, the interrupt mask flag should
be set to 1 before using the output mode.
Be sure to clear bits 0, 1, 6, and 7 to 0.
Before setting the INTM0 register, be sure to set the corresponding interrupt mask
flag (××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the
interrupt request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0),
which will enable interrupts.
Interrupt requests will be held pending while the interrupt request flag registers
(IF0) or interrupt mask flag registers (MK0) are being accessed.
F to the ANI0 to ANI3 pins (see Figure 9-19).
APPENDIX D LIST OF CAUTIONS
User’s Manual U16994EJ6V0UD
Cautions
μ
s after the ADCE bit
μ
F to 0.1
p. 174
p. 175
p. 175
p. 175
p. 175
pp. 180,
181
p. 182
p. 182
p. 184
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