UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 341

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Main clock OSTS:
Crystal/
ceramic
oscillator
16-bit
timer/
event
counter 00
Function
Oscillation
stabilization
time select
register
TM00: 16-bit
timer counter
00
CR000: 16-bit
timer capture/
compare
register 000
Details of
Function
−
To set and then release the STOP mode, set the oscillation stabilization time as
follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time
set by OSTS
The wait time after the STOP mode is released does not include the time from the
release of the STOP mode to the start of clock oscillation (“a” in the figure below),
regardless of whether STOP mode was released by reset input or interrupt
generation.
The oscillation stabilization time that elapses on power application or after release
of reset is selected by the option byte. For details, refer to CHAPTER 15 OPTION
BYTE.
When using the crystal/ceramic oscillator, wire as follows in the area enclosed by
the broken lines in Figure 5-6 to avoid an adverse effect from wiring capacitance.
Even if TM00 is read, the value is not captured by CR010.
When TM00 is read, count misses do not occur, since the input of the count clock
is temporarily stopped and then resumed after the read.
Set CR000 to other than 0000H in the clear & start mode entered on match
between TM00 and CR000. This means a 1-pulse count operation cannot be
performed when this register is used as an external event counter.
In the free-running mode and in the clear & start mode using the valid edge of the
TI000 pin, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated
when CR000 changes from 0000H to 0001H after an overflow (FFFFH).
If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00),
TM00 continues counting, overflows, and then starts counting from 0 again. If the
new value of CR000 is less than the old value, therefore, the timer must be reset
to be restarted after the value of CR000 is changed.
The value of CR000 after 16-bit timer/event counter 00 has stopped is not
guaranteed.
The capture operation may not be performed for CR000 set in compare mode
even if a capture trigger is input.
When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a
timer output pin (TO00). When using P21 as the timer output pin (TO00), it
cannot be used as the input pin (TI010) of the valid edge.
If the register read period and the input of the capture trigger conflict when CR000
is used as a capture register, the capture trigger input takes precedence and the
read data is undefined. Also, if the count stop of the timer and the input of the
capture trigger conflict, the capture trigger is undefined.
Changing the CR000 setting may cause a malfunction. To change the setting,
refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing
compare register during timer operation.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring
• Always make the ground point of the oscillator capacitor the same potential
• Do not fetch signals from the oscillator.
near a signal line through which a high fluctuating current flows.
as V
current flows.
SS
APPENDIX D LIST OF CAUTIONS
. Do not ground the capacitor to a ground pattern through which a high
User’s Manual U16994EJ6V0UD
Cautions
p. 78
p. 78
p. 78
p. 79
pp. 92,
124
pp. 92,
124
pp. 93,
124
pp.93,
124
pp. 93,
124
pp. 93,
125
pp. 93,
127
pp. 93,
100, 129
pp. 93,
126
p. 93
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