UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 242

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

240
(5) Flash address pointers H and L (FLAPH and FLAPL)
(6) Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and
FLAPLC)
These registers are used to specify the start address of the flash memory when the memory is erased, written,
or verified in the self programming mode.
FLAPH and FLAPL consist of counters, and they are incremented until the values match with those of
FLAPHC and FLAPLC when the programming command is not executed. When the programming command
is executed, therefore, set the value again.
These registers are set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation makes these registers undefined.
These registers are used to specify the address range in which the internal sequencer operates when the flash
memory is verified in the self programming mode.
Set FLAPHC to the same value as that of FLAPH. Set the last address of the range in which verification is to
be executed to FLAPLC.
These registers are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Caution Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H
Figure 16-15. Format of Flash Address Pointer H/L Compare Registers (FLAPHC/FLAPLC)
Cautions 1. Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self
Address: FFA4H, FFA5H
Address: FFA6H, FFA7H
0
0
0
0
compare register (FLAPHC) to 0 before executing the self programming command. If the
self programming command is executed with these bits set to 1, the device may malfunction.
3. Clear FLAPLC to 00H when a block erase is performed, and set this register to FFH
2. Set the number of the block subject to a block erase, verify, or blank check (same
Figure 16-14. Format of Flash Address Pointers H/L (FLAPH/FLAPL)
programming command.
programming command.
value as FLAPH) to FLAPHC.
when a blank check is performed.
0
0
FLAPHC (FFA6H)
FLAPH (FFA5H)
0
0
FLAP
FLA
P11
C11
After reset: Undefined
After reset: 00H
FLAP
FLA
P10
C10
CHAPTER 16 FLASH MEMORY
User’s Manual U16994EJ6V0UD
FLAP
FLA
P9
C9
FLAP
FLA
If the value of these bits is 1 when executing the self
P8
C8
R/W
FLAP
FLA
P7
C7
R/W
FLAP
FLA
P6
C6
FLAP
FLA
P5
C5
FLAPLC (FFA7H)
FLAPL (FFA4H)
FLAP
FLA
P4
C4
FLAP
FLA
P3
C3
FLAP
FLA
P2
C2
FLAP
FLA
P1
C1
FLAP
FLA
P0
C0