UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 240

• Manufacturer Part Number: UPD78F9212CS-CAB-A
• Description: MCU 8BIT 4KB FLASH 16PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9212CS-CAB-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

238
1. Operating conditions of FPRERR flag
2. Operating conditions of VCERR flag
3. Operating conditions of WEPRERR flag
<Setting conditions>
<Reset conditions>
<Setting conditions>
<Reset conditions>
<Setting conditions>
<Reset conditions>
If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to
write a specific value (A5H) to FLPMC
If the first store instruction operation after <1> is on a peripheral register other than FLPMC
If the first store instruction operation after <2> is on a peripheral register other than FLPMC
If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction
after <2>
If the first store instruction operation after <3> is on a peripheral register other than FLPMC
If a value other than the value to be set to FLPMC (value written in <2>) is written by the first store instruction
after <3>
Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command
If 0 is written to the FPRERR flag
If the reset signal is generation
Erasure verification error
Internal writing verification error
If VCERR is set, it means that the flash memory has not been erased or written correctly. Erase or write the
memory again in the specified procedure.
Remark The VCERR flag may also be set if an erase or write protect error occurs.
When 0 is written to the VCERR flag
When the reset signal generation
If the area specified by the protect byte to be protected from erasing or writing is specified by the flash
address pointer H (FLAPH) and a command is executed to this area
If 1 is written to a bit that has not been erased (a bit for which the data is 0).
When 0 is written to the WEPRERR flag
When the reset signal generation
Address: FFA1H
Symbol
PFS
register (PFCMD).
7
0
Figure 16-12. Format of Flash Status Register (PFS)
After reset: 00H
6
0
CHAPTER 16 FLASH MEMORY
User’s Manual U16994EJ6V0UD
5
0
R/W
4
0
3
0
WEPRERR
2
VCERR
1
FPRERR
0