UPD78F9212CS-CAB-A Renesas Electronics America, UPD78F9212CS-CAB-A Datasheet - Page 262
UPD78F9212CS-CAB-A
Manufacturer Part Number
UPD78F9212CS-CAB-A
Description
MCU 8BIT 4KB FLASH 16PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9510GR-JJG-A.pdf
(364 pages)
Specifications of UPD78F9212CS-CAB-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
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Example programs that perform internal verify 1 and 2 in self programming mode are shown below.
;----------------------------
;START
;----------------------------
FlashVerify:
;----------------------------
;END
;----------------------------
;----------------------------
;START
;----------------------------
FlashVerify:
;----------------------------
;END
;----------------------------
Internal verify 1
Internal verify 2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
HALT
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
HALT
MOV
MOV
FLCMD,#01H
FLAPH,#07H
FLAPL,#00H
FLAPHC,#07H
FLAPLC,#FFH
PFS,#00H
WDTE,#0ACH
A,PFS
CmdStatus,A
FLCMD,#02H
FLAPH,#07H
FLAPL,#00H
FLAPHC,#07H
FLAPLC,#20H
PFS,#00H
WDTE,#0ACH
A,PFS
CmdStatus,A
; Sets flash control command (internal verify 1)
; Sets block number for which internal verify is performed,
; to FLAPH (Example: Block 7 is specified here)
; Sets 00H
; Sets FFH
; Clears flash status register
; Clears & restarts WDT
; Self programming is started
; Execution result is stored in variable
; (CmdStatus = 0: normal termination, other than 0: abnormal
; termination)
; Sets flash control command (internal verify 2)
; Sets block number for which internal verify is
; performed, to FLAPH (Example: Block 7 is specified here)
; Sets FLAPL to the start address for verify (Example: Address
; 00H is specified here)
; Sets FLAPLC to the end address for verify (Example: Address
; 20H is specified here)
; Clears flash status register
; Clears & restarts WDT
; Self programming is started
; Execution result is stored in variable
; (CmdStatus = 0: normal termination, other than 0: abnormal
; termination)
CHAPTER 16 FLASH MEMORY
User’s Manual U16994EJ6V0UD
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