EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 150

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

7–2
Cyclone IV Devices Memory Interfaces Pin Support
Data and Data Clock/Strobe Pins
Cyclone IV Device Handbook, Volume 1
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For more information about implementing complete external memory interfaces, refer
to the
Cyclone IV devices use data (DQ), data strobe (DQS), clock, command, and address
pins to interface with external memory. Some memory interfaces use the data mask
(DM) or byte write select (BWS#) pins to enable data masking. This section describes
how Cyclone IV devices support all these different pins.
For more information about pin utilization, refer to
Layout Guidelines
Cyclone IV data pins for external memory interfaces are called D for write data, Q for
read data, or DQ for shared read and write data pins. The read-data strobes or read
clocks are called DQS pins. Cyclone IV devices support both bidirectional data strobes
and unidirectional read clocks. Depending on the external memory standard, the DQ
and DQS are bidirectional signals (in DDR2 and DDR SDRAM) or unidirectional
signals (in QDR II SRAM). Connect the bidirectional DQ data signals to the same
Cyclone IV devices DQ pins. For unidirectional D or Q signals, connect the read-data
signals to a group of DQ pins and the write-data signals to a different group of DQ
pins.
In QDR II SRAM, the Q read-data group must be placed at a different V
location from the D write-data group, command, or address pins.
In Cyclone IV devices, DQS is used only during write mode in DDR2 and
DDR SDRAM interfaces. Cyclone IV devices ignore DQS as the read-data strobe
because the PHY internally generates the read capture clock for read mode. However,
you must connect the DQS pin to the DQS signal in DDR2 and DDR SDRAM
interfaces, or to the CQ signal in QDR II SRAM interfaces.
Cyclone IV devices do not support differential strobe pins, which is an optional
feature in the DDR2 SDRAM device.
When you use the Altera Memory Controller MegaCore
instantiated for you. For more information about the memory interface data path,
refer to the
ALTMEMPHY is a self-calibrating megafunction, enhanced to simplify the
implementation of the read-data path in different memory interfaces. The
auto-calibration feature of ALTMEMPHY provides ease-of-use by optimizing clock
phases and frequencies across process, voltage, and temperature (PVT) variations.
You can save on the global clock resources in Cyclone IV devices through the
ALTMEMPHY megafunction because you are not required to route the DQS signals
on the global clock buses (because DQS is ignored for read capture).
Resynchronization issues do not arise because no transfer occurs from the memory
domain clock (DQS) to the system domain for capturing data DQ.
External Memory Interface
External Memory Interface
of the External Memory Interface Handbook.
Handbook.
Handbook.
Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Pin Support
Volume 2: Device, Pin, and Board
®
function, the PHY is
© December 2010 Altera Corporation
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