EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 337

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Figure 1–57. Example of Reset Condition in GIGE Mode
© December 2010 Altera Corporation
tx_digitalreset
tx_dataout
clock
K28.5
Running Disparity Preservation with Idle Ordered Set
During idle ordered sets transmission in GIGE mode, the transmitter ensures a
negative running disparity at the end of an idle ordered set. Any /Dx.y/, except for
/D21.5/ (part of /C1/ ordered set) or /D2.2/ (part of /C2/ ordered set) following a
/K28.5/ is automatically replaced with either of the following:
■
■
Lane Synchronization
In GIGE mode, the word aligner is configured in automatic synchronization state
machine mode that complies with the IEEE P802.3ae standard. A synchronization
ordered set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code
groups.
implements the GbE-compliant synchronization.
Table 1–19. Synchronization State Machine Parameters
Clock Frequency Compensation
In GIGE mode, the rate match FIFO compensates up to ±100 PPM (200 PPM total)
difference between the upstream transmitter and the local receiver reference clock.
The GIGE protocol requires the transmitter to send idle ordered sets /I1/
(/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps, adhering to the
rules listed in the IEEE 802.3 specification.
The rate match operation begins after the synchronization state machine in the word
aligner indicates synchronization has been acquired by driving the rx_syncstatus
signal high. The rate match FIFO deletes or inserts both symbols of the /I2/ ordered
sets (/K28.5/ and /D16.2/) to prevent the rate match FIFO from overflowing or
underflowing. It can insert or delete as many /I2/ ordered sets as necessary to
perform the rate match operation.
Number of valid synchronization ordered sets received to achieve
synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by
one
Note to
(1) The word aligner supports 7-bit and 10-bit pattern lengths in GIGE mode.
xxx
A /D5.6/ (/I1/ ordered set) if the running disparity before /K28.5/ is positive
A /D16.2/ (/I2/ ordered set) if the running disparity before /K28.5/ is negative
Table
Table 1–19
K28.5
1–19:
K28.5
lists the synchronization state machine parameters that
n
K28.5
n + 1
Dx.y
Parameter
n + 2
Dx.y
n + 3
K28.5
n + 4
Dx.y
(Note 1)
K28.5
Cyclone IV Device Handbook, Volume 2
Dx.y
K28.5
Dx.y
Value
3
4
4
1–57