EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 418

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

3–28
Figure 3–12. Option 2 for Transmitter Core Clocking (Channel Reconfiguration Mode)
Cyclone IV Device Handbook, Volume 2
FPGA Fabric
tx_clkout[0]
tx_clkout[1]
tx_clkout[2]
tx_clkout[3]
Low-speed parallel clock
High-speed serial clock generated by the MPLL
Figure 3–12
clock to the Transmit Phase Compensation FIFOs of the respective transceiver
channels.
Receiver core clocking refers to the clock that is used to read the parallel data from the
Receiver Phase Compensation FIFO into the FPGA fabric. You can use one of the
following clocks to read from the Receive Phase Compensation FIFO:
■
■
Option 1: Share a Single Transmitter Core Clock Between Receivers
■
■
rx_coreclk—you can use a clock of the same frequency as rx_clkout from the
FPGA fabric to provide the read clock to the Receive Phase Compensation FIFO. If
you use rx_coreclk, it overrides the rx_clkout options in the ALTGX
MegaWizard Plug-In Manager.
rx_clkout—the Quartus II software automatically routes rx_clkout to the
FPGA fabric and back into the Receive Phase Compensation FIFO.
Enable this option if you want tx_clkout of the first channel (channel 0) of the
transceiver block to provide the read clock to the Receive Phase Compensation
FIFOs of the remaining receiver channels in the transceiver block.
This option is typically enabled when all the channels of a transceiver block are in
a Basic or Protocol configuration with rate matching enabled and are reconfigured
to another Basic or Protocol configuration with rate matching enabled.
shows how each transmitter channel’s tx_clkout signal provides a
Transciever Block
RX0
RX1
RX2
RX3
TX0
TX1
TX2
TX3
Chapter 3: Cyclone IV Dynamic Reconfiguration
© December 2010 Altera Corporation
MPLL
Dynamic Reconfiguration Modes