EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 195

no-image

EP4CE55F23C8

Manufacturer Part Number
EP4CE55F23C8
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er

Specifications of EP4CE55F23C8

Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CE55F23C8
Manufacturer:
ALTERA
Quantity:
784
Part Number:
EP4CE55F23C8
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP4CE55F23C8
Manufacturer:
ALTERA
0
Part Number:
EP4CE55F23C8L
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP4CE55F23C8LN
Manufacturer:
ALTERA
Quantity:
364
Part Number:
EP4CE55F23C8LN
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP4CE55F23C8LN
Manufacturer:
ALTERA
0
Part Number:
EP4CE55F23C8LN
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP4CE55F23C8N
Manufacturer:
ALTERA
Quantity:
852
Part Number:
EP4CE55F23C8N
Manufacturer:
ALTERA
Quantity:
20 000
Part Number:
EP4CE55F23C8N
0
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
Figure 8–11
interfaces to minimize signal integrity issues.
Figure 8–11. Balanced Star Routing
Notes to
(1) Altera recommends that M does not exceed 6 inches, as listed in
(2) Altera recommends using a balanced star routing. Keep the N length equal and as short as possible to minimize
Estimating AP Configuration Time
AP configuration time is dominated by the time it takes to transfer data from the
parallel flash to Cyclone IV E devices. This parallel interface is clocked by the
Cyclone IV E DCLK output (generated from an internal oscillator). The DCLK
minimum frequency when using the 40-MHz oscillator is 20 MHz (50 ns). In
word-wide cascade programming, the DATA[15..0] bus transfers a 16-bit word and
essentially cuts configuration time to approximately 1/16 of the AS configuration
time.
Equation 8–4.
Equation 8–5.
RBF Size
reflection noise from the transmission line. The M length is applicable for this setup.
Equation 8–4
Figure
maximum DCLK period
------------------------------------------------------ -
16 bits per DCLK cycle
shows the recommended balanced star routing for multiple bus master
8–11:
and
Master Device
Cyclone IV E
Equation 8–5
DCLK
9,600,000 bits
=
estimated maximum configuration time
show the configuration time calculations.
M (1)
50 ns
------------ -
16 bit
=
Table 8–9 on page
30 ms
Numonyx Flash
Master Device
External
Cyclone IV Device Handbook, Volume 1
N (2)
N (2)
8–27.
8–29

Related parts for EP4CE55F23C8