EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 211

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Table 8–12. Dedicated JTAG Pins
© December 2010 Altera Corporation
TDI
TDO
TMS
TCK
Pin Name
f
Test data
input
Test data
output
Test mode
select
Test clock
input
Pin Type
For more information about the JTAG boundary-scan testing, refer to the
Boundary-Scan Testing for Cyclone IV Devices
JTAG instructions have precedence over any other configuration modes. Therefore,
JTAG configuration can take place without waiting for other configuration modes to
complete. For example, if you attempt JTAG configuration in Cyclone IV devices
during PS configuration, PS configuration terminates and JTAG configuration begins.
If the MSEL pins are set to AS mode, the Cyclone IV device does not output a DCLK
signal when JTAG configuration takes place.
The four required pins for a device operating in JTAG mode are TDI, TDO, TMS, and
TCK. All the JTAG input pins are powered by the V
I/O standard only. All user I/O pins are tri-stated during JTAG configuration.
Table 8–12
You can download data to the device through the USB-Blaster, MasterBlaster,
ByteBlaster II, or ByteBlasterMV download cable, or the EthernetBlaster
communications cable during JTAG configuration. Configuring devices with a cable is
similar to programming devices in-system.
JTAG configuration of a single Cyclone IV device.
For device using V
maintain a maximum AC voltage of 4.1 V because JTAG pins do not have the internal
PCI clamping diodes to prevent voltage overshoot when using V
3.3 V. You must power up the V
V
up the V
CCA
. For device using V
Serial input pin for instructions as well as test and programming data. Data shifts in on the
rising edge of
disabled by connecting this pin to V
k).
Serial data output pin for instructions as well as test and programming data. Data shifts out on
the falling edge of
JTAG interface is not required on the board, the JTAG circuitry is disabled by leaving this pin
unconnected.
Input pin that provides the control signal to determine the transitions of the TAP controller
state machine. Transitions in the state machine occur on the rising edge of
TMS must be set up before the rising edge of TCK . TMS is evaluated on the rising edge of
TCK . If the JTAG interface is not required on the board, the JTAG circuitry is disabled by
connecting this pin to V
The clock input to the BST circuitry. Some operations occur at the rising edge, while others
occur at the falling edge. If the JTAG interface is not required on the board, the JTAG circuitry
is disabled by connecting this pin to GND. The TCK pin has an internal weak pull-down
resistor.
CC
explains the function of each JTAG pin.
of the download cable with the supply from V
TCK . If the JTAG interface is not required on the board, the JTAG circuitry is
CCIO
TCK . The pin is tri-stated if data is not being shifted out of the device. If the
of 2.5, 3.0, and 3.3 V, refer to
CCIO
CC
. TMS pin has weak internal pull-up resistors (typically 25 k).
of 1.2, 1.5, and 1.8 V, refer to
CC
of the download cable with a 2.5-V supply from
CC
. TDI pin has weak internal pull-up resistors (typically 25
Description
Figure 8–23
chapter.
CCIO
Figure
pin and support the LVTTL
and
Figure
CCIO
Cyclone IV Device Handbook, Volume 1
8–23. All I/O inputs must
Figure 8–24
.
8–24. You can power
CCIO
of 2.5, 3.0, and
TCK . Therefore,
show the
JTAG
8–45