EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 379

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Figure 2–8. Sample Reset Sequence of Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
Notes to
(1) For t
(2) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
© December 2010 Altera Corporation
Output Status Signals
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
LTD_Auto
Figure
rx_analogreset
Reset Signals
rx_digitalreset
tx_digitalreset
rx_freqlocked
pll_locked
pll_areset
duration, refer to the
2–8:
busy (2)
1
Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and a receiver channel. If you create a
Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with
the receiver CDR in automatic lock mode, use the reset sequence shown in
As shown in
CDR automatic lock mode:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset
3. After the multipurpose PLL locks, as indicated by the pll_locked signal going
4. Wait for the rx_freqlocked signal to go high (marker 7).
between markers 1 and 2).
signals asserted during this time period. After you deassert the pll_areset
signal, the multipurpose PLL starts locking to the transmitter input reference
clock.
high (marker 3), deassert tx_digitalreset. For receiver operation, after
deassertion of busy signal, wait for two parallel clock cycles to deassert the
rx_analogreset signal.
1 µs
Cyclone IV Device Datasheet
2
Figure
2–8, perform the following reset procedure for the receiver in
3
Two parallel clock cycles
4
5
chapter.
6
7
t
LTD_Auto
(1)
8
Cyclone IV Device Handbook, Volume 2
Figure
2–8.
2–13