EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 240

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

8–74
Table 8–20. Remote System Upgrade Registers
Cyclone IV Device Handbook, Volume 1
Shift
register
Control
register
Update
register
Status
register
Register
This register is accessible by the logic array and allows the update, status, and control registers to be written
and sampled by user logic. Write access is enabled in remote update mode for factory configurations to allow
writing to the update register. Write access is disabled for all application configurations in remote update mode.
This register contains the current configuration address, the user watchdog timer settings, one option bit for
checking early CONF_DONE, and one option bit for selecting the internal oscillator as the startup state
machine clock. During a read operation in an application configuration, this register is read into the shift
register. When a reconfiguration cycle is started, the contents of the update register are written into the control
register.
This register contains data similar to that in the control register. However, it can only be updated by the factory
configuration by shifting data into the shift register and issuing an update operation. When a reconfiguration
cycle is triggered by the factory configuration, the control register is updated with the contents of the update
register. During a read in a factory configuration, this register is read into the shift register.
This register is written by the remote system upgrade circuitry on every reconfiguration to record the cause of
the reconfiguration. This information is used by the factory configuration to determine the appropriate action
following a reconfiguration. During a capture cycle, this register is read into the shift register.
Remote System Upgrade Registers
The remote system upgrade block contains a series of registers that stores the
configuration addresses, watchdog timer settings, and status information.
lists these registers.
The control and status registers of the remote system upgrade are clocked by the
10-MHz internal oscillator (the same oscillator that controls the user watchdog timer)
or the CLKUSR. However, the shift and update registers of the remote system upgrade
are clocked by the maximum frequency of 40-MHz user clock input (RU_CLK). There
is no minimum frequency for RU_CLK.
Remote System Upgrade Control Register
The remote system upgrade control register stores the application configuration
address, the user watchdog timer settings, and option bits for a application
configuration. In remote update mode for the AS configuration scheme, the control
register address bits are set to all zeros (24'b0) at power up to load the AS factory
configuration. In remote update mode for the AP configuration scheme, the control
register address bits are set to 24'h010000 (24'b1 0000 0000 0000 0000) at power
up to load the AP default factory configuration. However, for the AP configuration
scheme, you can change the default factory configuration address to any desired
address using the APFC_BOOT_ADDR JTAG instruction. Additionally, a factory
configuration in remote update mode has write access to this register.
Figure 8–34
register bit contents. The numbers in
register. For example, bit number 35 is the enable bit for the watchdog timer.
shows the control register bit positions.
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Description
Figure 8–34
show the bit position of a setting in a
Table 8–21
© December 2010 Altera Corporation
defines the control
Remote System Upgrade
Table 8–20