EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 326

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–46
.
Figure 1–47. Transceiver Channel Datapath in Basic Mode with Low-Latency PCS Operation
Cyclone IV Device Handbook, Volume 2
Fabric
FPGA
1
1
Figure 1–47
PCS operation.
Transmitter in Electrical Idle
The transmitter buffer supports electrical idle state, where when enabled, the
differential output buffer driver is tri-stated. During electrical idle, the output buffer
assumes the common mode output voltage levels. For details about the electrical idle
features, refer to
The transmitter in electrical idle feature is required for compliance to the version 2.00
of PHY Interface for the PCI Express (PIPE) Architecture specification for PCIe
protocol implementation.
Signal Detect at Receiver
Signal detect at receiver is only supported when 8B/10B encoder/decoder block is
enabled.
Receiver Spread Spectrum Clocking
The CDR supports optional wider spread of asynchronous SSC (triangular frequency
modulation profile only) in EP4CGX30 (F484 package), EP4CGX50, and EP4CGX75
devices only. You can turn on the SSC input clocking tracking capability on the
receiver channel by checking the Enable the Spread Spectrum feature option in the
'Rx Analog' page of the ALTGX Megawizard.
You should use different MPLLs to clock your TX and RX channel separately, if you
plan to use spread spectrum clocking modulation on the transmitter side. This is to
ensure the input reference clock to the RX channel is not SSC modulated. You can
separate the TX and RX MPLLs by instantiating the TX only and RX only modes in
the 'What is the operation mode?' setting in the ALTGX Megawizard and connect two
separate input reference clocks to the TX only and RX only channels respectively.
The following describes the SATA, V-by-One, and Display Port protocol support
using Basic mode.
Phase
Comp
FIFO
Rx
shows the transceiver channel datapath in Basic mode with low-latency
wr_clk
Tx Phase
Comp
FIFO
“PCI Express (PIPE) Mode” on page
rd_clk
Order-
Byte
ing
serializer
Byte
De-
wr_clk
Byte Serializer
Transmitter Channel PCS
Decoder
8B/10B
rd_clk
Receiver Channel PCS
Match
Rate
FIFO
Chapter 1: Cyclone IV Transceivers Architecture
8B/10B Encoder
1–48.
Deskew
FIFO
© December 2010 Altera Corporation
Transceiver Functional Modes
Aligner
Word
Deserial-
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
CDR