EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 374

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–8
Cyclone IV Device Handbook, Volume 2
As shown in
in automatic lock mode configuration:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset
3. After the multipurpose PLL locks, as indicated by the pll_locked signal going
4. For the receiver operation, after deassertion of busy signal, wait for two parallel
5. Wait for the rx_freqlocked signal from each channel to go high. The
6. In a bonded channel group, when the rx_freqlocked signals of all the channels
between markers 1 and 2).
signals asserted during this time period. After you deassert the pll_areset
signal, the multipurpose PLL starts locking to the input reference clock.
high, deassert the tx_digitalreset signal. At this point, the transmitter is
ready for data traffic.
clock cycles to deassert the rx_analogreset signal.
rx_freqlocked signal of each channel may go high at different times (indicated
by the slashed pattern at marker 7).
has gone high, from that point onwards, wait for at least t
receiver parallel clock to be stable, then deassert the rx_digitalreset signal
(marker 8). At this point, all the receivers are ready for data traffic.
Figure
2–4, perform the following reset procedure for the receiver CDR
Chapter 2: Cyclone IV Reset Control and Power Down
© December 2010 Altera Corporation
LTD_Auto
Transceiver Reset Sequences
time for the