EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 358

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–78
Table 1–25. PRBS, High and Low Frequency Patterns, and Channel Settings
Cyclone IV Device Handbook, Volume 2
Patterns
PRBS 7
PRBS 8
PRBS 10
PRBS 23
High
frequency
Low
Frequency
(2)
Notes to
(1) Channel width refers to the What is the channel width? option in the General screen of the ALTGX MegaWizard Plug-In Manager. Based on the
(2) A verifier and associated rx_bistdone and rx_bisterr signals are not available for the specified patterns.
selection, an 8 or 10 bits wide pattern is generated as indicated by a Yes (Y) or No (N).
Table
(2)
1–25:
Polynomial
X
1010101010
1111100000
X
X
X
23
10
7
8
+ X
+ X
+ X
+ X
6
7
18
Table 1–25
corresponding channel settings. The PRBS pattern repeats after completing an
iteration. The number of bits a PRBS X pattern sends before repeating the pattern is
2
You can enable the serial loopback option to loop the generated PRBS patterns to the
receiver channel for verifier to check the PRBS patterns. When the PRBS pattern is
received, the rx_bisterr and rx_bistdone signals indicate the status of the
verifier. After the word aligner restores the word boundary, the rx_bistdone signal
is driven high when the verifier receives a complete pattern cycle and remains
asserted until it is reset using the rx_digitalreset port. After the assertion of
rx_bistdone, the rx_bisterr signal is asserted for a minimum of three
rx_clkout cycles when errors are detected in the data and deasserts if the following
PRBS sequence contains no error. You can reset the PRBS pattern generator and
verifier by asserting the tx_digitalreset and rx_digitalreset ports,
respectively.
7
(X-1)
+ 1
+ 1
+ 1
+ 1
bits.
Channel
Width
8 bits
(1)
of
N
N
Y
Y
Y
Y
lists the supported PRBS, high and low frequency patterns, and
Alignment
16’h3040
16’hFF5A
16’hFFFF
Pattern
8-bit Channel Width
Word
—
—
—
Maximum
Data Rate
(Gbps) for
Packages
F324 and
Smaller
2.0
2.0
2.0
2.0
—
—
Maximum
Data Rate
(Gbps) for
Packages
F484 and
Larger
2.5
2.5
2.5
2.5
—
—
Channel
10-bits
Width
Chapter 1: Cyclone IV Transceivers Architecture
(1)
of
N
N
Y
N
Y
Y
Alignment
© December 2010 Altera Corporation
10’h3FF
Pattern
10-bit Channel Width
Word
—
—
—
—
—
Data Rate
(Gbps) for
Packages
Maximum
F324 and
Smaller
2.5
2.5
2.5
—
—
—
Self Test Modes
Maximum
Data Rate
(Gbps) for
Packages
F484 and
Larger
3.125
3.125
3.125
—
—
—