EP4CE55F23C8 Altera, EP4CE55F23C8 Datasheet - Page 295

• Manufacturer Part Number: EP4CE55F23C8
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
Word Aligner
© December 2010 Altera Corporation
Figure 1–16
data from the deserializer and restores the word boundary based on a pre-defined
alignment pattern that must be received during link synchronization. The word
aligner supports three operational modes as listed in
Figure 1–16. Word Aligner Block Diagram
Table 1–3. Word Aligner Modes
Manual Alignment Mode
In manual alignment mode, the rx_enapatternalign port controls the word
aligner with either an 8- or 10-bit data width setting.
The 8-bit word aligner is edge-sensitive to the rx_enapatternalign signal. A
rising edge on rx_enapatternalign signal after deassertion of the
rx_digitalreset signal triggers the word aligner to look for the word alignment
pattern in the received data stream. It updates the word boundary if it finds the word
alignment pattern in a new word boundary. Any word alignment pattern received
thereafter in a different word boundary causes the word aligner to re-align to the new
word boundary only if there is a rising edge in the rx_enapatternalign signal.
The 10-bit word aligner is level-sensitive to the rx_enapatternalign signal. The
word aligner looks for the programmed 7-bit or 10-bit word alignment pattern in the
received data stream, if the rx_enapatternalign signal is held high. It updates the
word boundary if it finds the word alignment pattern in a new word boundary. If the
rx_enapatternalign signal is deasserted, the word aligner maintains the current
word boundary even when it receives the word alignment pattern in a new word
boundary.
Manual Alignment
Bit-Slip
Automatic Synchronization State
Machine
rx_enapatternalign
rx_revbitorderwa
rx_invpolarity
deserializer
data from
rx_bitslip
shows the word aligner block diagram. The word aligner receives parallel
Modes
Word Aligner
Receiver
Inversion
Polarity
PMA-PCS Interface Widths
Synchronization
State Machine
Run Length
Alignment
Violation
Circuitry
Manual
Bit-Slip
10-bit
10-bit
10-bit
8-bit
8-bit
Table
Receiver
Reversal
Bit
Cyclone IV Device Handbook, Volume 2
1–3.
Allowed Word Alignment
Pattern Lengths
7 or 10 bits
7 or 10 bits
7 or 10 bits
16 bits
16 bits
rx_bitslipboundaryselectout
rx_rlv
rx_syncstatus
rx_patterndetect
parallel data to
next PCS block
1–15