MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 24

• Manufacturer Part Number: MCZ33905S5EK
• Description: IC SYSTEM BASIS CHIP GEN2 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905S5EK

• Applications: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. Dynamic Electrical Characteristics
values noted reflect the approximate parameter means at T
24
STATE DIGRAM TIMINGS
CAN DYNAMIC CHARACTERISTICS
Notes
33903/4/5
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Delay for SPI Timer A, Timer B or Timer C write command after entering Normal
mode
(No command should occur within t
t
command to CS falling edge of “Timer write” command)
Tolerance for: W/D period in all modes, FWU delay, Cyclic sense period and
active time, Cyclic Interrupt period, LP mode over-current (unless otherwise
noted)
TXD Dominant State Timeout
Bus dominant clamping detection
Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate)
Propagation delay TXD to CAN, recessive to dominant
Propagation delay CAN to RXD, recessive to dominant
Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate)
Propagation delay TXD to CAN, dominant to recessive
Propagation delay CAN to RXD, dominant to recessive
Loop time TXD to RXD, Medium Slew rate (Selected by SPI)
Loop time TXD to RXD, Slow Slew rate (Selected by SPI)
CAN wake-up filter time, single dominant pulse detection
CAN wake-up filter time, 3 dominant pulses detection
CAN wake-up filter time, 3 dominant pulses detection timeout
Figure
19.
20.
21.
22.
D_NM
Characteristics noted under conditions 5.5 V ≤ V
Rec to Dom
Dom to Rec
Rec to Dom
Dom to Rec
delay definition: from CS rising edge of "Go to Normal mode (i.e 0x5A00)"
(22)
No wake-up for single pulse shorter than t
Each pulse should be greater than t
The 3 pulses should occur within t
Guaranteed by design.
33)
Characteristic
D_NM
.
CAN-WU3-TO
CAN-WU3-F
CAN-WU1
. Guaranteed by design, and device characterization.
min. Guaranteed by design, and device characterization.
(20)
SUP
(19)
min. Wake-up for single pulse longer than t
≤ 27 V, - 40 °C ≤ T
(See
(21)
(See
A =
Figure
25 °C under nominal conditions, unless otherwise noted.
32)
A
t
t
TIMING-ACC
t
t
CAN-WU3-TO
t
t
CAN-WU1-F
CAN-WU3-F
≤ 125 °C, GND = 0 V, unless otherwise noted. Typical
LOOP-MSL
LOOP-SSL
Symbol
t
t
t
D_NM
DOUT
t
t
t
t
t
t
DOM
LRD
TRD
RRD
LDR
TDR
RDR
Min
300
300
100
300
-10
0.5
60
60
Analog Integrated Circuit Device Data
-
-
-
-
-
-
-
-
-
CAN-WU1
max.
Typ
600
600
120
120
200
200
300
300
2.0
70
45
75
50
-
-
-
-
Freescale Semiconductor
1000
1000
Max
210
140
200
150
140
120
110
5.0
10
-
-
-
-
-
-
Unit
μs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
μs
%