MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 43

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MCZ33905S5EK

Manufacturer Part Number
MCZ33905S5EK
Description
IC SYSTEM BASIS CHIP GEN2 32SOIC
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MCZ33905S5EK

Applications
System Basis Chip
Interface
CAN, LIN
Voltage - Supply
5.5 V ~ 27 V
Package / Case
32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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DEVICE POWER UP:
and ramp down of V
the Crank bit and the two V
DEVICE POWER DOWN
V
under-voltage reset selection.
Crank bit reset (INIT W/D register, bit 0 =0):
enters in Reset mode due to a V
Analog Integrated Circuit Device Data
Freescale Semiconductor
SUP1
This section describe the device behavior during ramp up,
D1
The figures below illustrate the device behavior during
Bit 0 = 0 is the default state for this bit.
During V
ramp down, based on Crank bit configuration, and V
V
VSUP1
BAT
SUP
ramp down, V
MC33905
SUP1
, and the flexibility offered mainly by
Gnd
DD
under-voltage reset thresholds.
DD
DD
remain ON until device
VDD
BEHAVIOR AT POWER UP AND POWER DOWN
under-voltage condition
Figure 25. V
I
_VDD
VSUP1
VDD
RESET
DD
Start-up Versus V
DD
V
SUP_TH1
V
enable when V
(V
SPI). When device is in Reset, if V
V
Crank bit set (INIT Watchdog register, bit 0 =1):
remains ON until device detects a POR and set BATFAIL.
This occurs for a V
SUP1
DD
V
DD
The figures below illustrate the device behavior during
The bit 0 is set by SPI write. During V
SUP
is turned OFF.
< 4.6 V or V
slew rate
ramp up. As the Crank bit is by default set to 0, V
SUP1
Tramp
BEHAVIOR AT POWER UP AND POWER DOWN
SUP1
DD
SUP
V
is above V
V
< 3.2 V typ, threshold selected by the
DD_OFF
10% V
DD_START UP
90% V
approx 3.0 V.
FUNCTIONAL DEVICE OPERATION
DD_START UP
DD_START UP
1.0 ms
SUP TH 1
V
V
DD_UV TH
DD NOMINAL
V
SUP
SUP_NOMINAL
is below “V
SUP
parameters.
(typ 4.65 V)
ramp down, V
(ex 5.0 V)
(ex 12 V)
SUP_TH1
33903/4/5
DD
DD
43
”,
is

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