MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 46

• Manufacturer Part Number: MCZ33905S5EK
• Description: IC SYSTEM BASIS CHIP GEN2 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905S5EK

• Applications: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
Conditions to set SAFE pin active low:
or at the second consecutive reset pulse (selected by bit 4,
INIT W/D register).
46
33903/4/5
FAIL SAFE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
Watchdog refresh issue: SAFE activated at 1st reset pulse
SAFE pin release
(SAFE high)
Failure events
Device state:
Legend:
1) bit 4 of INIT Watchdog register
2) Wake-up event: CAN, LIN or I/O-1 high level (if I/O-1 wake-up previously enabled)
3) SPI commands: 0xDD00 or 0xDD80 to release SAFE pin
4) Recovery: reset low condition released, V
5) detection of 8 consecutive W/D failures: no correct SPI W/D refresh command occurred for duration of 8 x 256 ms.
6) Dynamic behavior: 1.0 ms reset pulse every 256 ms, due to no W/D refresh SPI command, and device state transition
between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes.
7) 8 second timer for bus idle timeout. I/O-1 high to low transition.
SPI (3)
Normal Request
Normal, FLASH
RESET
INIT,
W/D failure
bit 4, INIT W/D = 1 (1)
bit 4, INIT W/D = 0 (1)
Rst s/c gnd:
Rst <2.5 V, t >100 ms
V
V
DD
DD
low:
<V
DD
_
UVTH
DD
low condition released, correct SPI W/D refresh
Figure 27. Safe Operation Flow Chart
RESET
- Reset low
- SAFE low
- V
SAFE high
SAFE low
DD
SAFE Operation Flow Chart
ON
8 consecutive W/D failure (5)
at DBG pin during
a) Evaluation of
Resistor detected
power up, or SPI
register content
- I/O-1 monitoring
b) ECU external signal
monitoring (7):
- bus idle time out
Reset: 1.0 ms pulse
Reset: 1.0 ms pulse
as the RESET pin is set low.
clamped to a low level preventing the MCU to operate. If this
is the case, the Safe mode is entered.
V
The RESET pin is monitored to verify that reset is not
DD
Wake-up (2), V
low: V
detection of 2nd
consecutive W/D failure
DD
State B2:
R
State B1: R
Bus idle timeout expired
State B3:
R
AND Bus idle time out expired
State A: R
(V
State A: R
W/D failure
DBG
DBG
failure recovery, SAFE pin remains low
DD
<
DD
SAFE low
low or R
= 33 k AND I/O-1 low
R
= 47 k AND I/O-1 low
ST-TH
ON, SAFE pin remains low
DBG
Analog Integrated Circuit Device Data
DBG
DBG
. SAFE pin is set low at same time
ST
<6.0 k AND
<6.0 k AND
= 15 k AND
s/c GND) failure
RESET
Freescale Semiconductor
- SAFE low
- Reset low
- V
- SAFE low
- V
- Reset: 1.0 ms
periodic pulse
- SAFE low
- V
- Reset low
(6)
DD
DD
DD
OFF
ON
ON
NR