MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 64

• Manufacturer Part Number: MCZ33905S5EK
• Description: IC SYSTEM BASIS CHIP GEN2 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905S5EK

• Applications: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 16. Initialization Watchdog Registers, INIT W/D (note: register can be written only in INIT mode)
no W/D + 00
no W/D + 01
no W/D + 10
no W/D + 11 In Low Power V
W/D + 00
W/D + 01
W/D + 10
W/D + 11
[b_15 b_14] 0_0110 [P/N]
b6, b5
b3, b2
MOSI First Byte [15-8]
Bit
Condition for default
b7
b4
00
01
10
11
b1
b0
0
1
0
1
0
1
0
1
01 00 _ 110 P
Default state
MCU_OC, OC-TIM - In Low Power V
In Low Power V
threshold for a time > I_mcu_OC is wake-up event. I_mcu_OC time is selected in Timer register (selection range from 3.0 to 32 ms)
In Low Power V
In Low Power V
DD
DD
In Low Power V
ON mode, V
INT source read must occur before the remaining of the current W/D period plus 2 complete W/D periods.
ON mode, V
WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command
WD2INT
Watchdog operation is WINDOW, W/D refresh must occur in the open window (second half of period)
bit 7
WD Safe - Select the activation of the SAFE pin low, at first or second consecutive RESET pulse
0
V
In Low Power V
DD
DD
DD
Crank - Select the V
Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.
Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command.
ON mode, V
ON mode, V
disable when V
DD
DD
Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits.
Watchdog operation is TIMEOUT, W/D refresh can occur anytime in the period
Function disable. No constraint between INT occurrence and INT source read.
DD
current > V
MCU_OC
current > V
ON mode, V
Simple Watchdog selection: W/D refresh done by a 8 bits or 16 bits SPI
DD
WD N/Win - Select the Watchdog (W/D) Window or Timeout operation
bit 6
V
SAFE pin is set low at the second consecutive time RESET pulse
1
ON, select watchdog refresh and V
DD
SAFE pin is set low at the time of the RESET pin low activation
WD_spi[1] WD_spi[0] - Select the Watchdog (W/D) Operation
In Low Power V
In Low Power V
DD
DD
DD
kept ON when V
DD_OC_LP
ON mode, V
current > V
current > V
SUP1
DD_OC_LP
DD
In low power mode, when W/D is not selected
device electrical parameters (approx 1.5 mA)
SUP1
register (selection range from 3.0 to 32 ms)
is below typ 4.0 V (parameter V
OC-TIM
In low power mode when W/D is selected
current > V
bit 5
0
threshold to disable V
threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer
DD_OC_LP
DD_OC_LP
threshold for a time < I_mcu_OC is a W/D refresh condition. V
DD
DD
DD
SUP1
ON mode, V
ON mode, V
over-current for a time > 100 μs (typ) is a wake-up event.
DD_OC_LP
Description
is below typ 4.0 V (parameter V
WD Safe
MOSI Second Byte, bits 7-0
threshold has no effect. W/D refresh must occur by SPI command.
threshold has no effect. W/D refresh must occur by SPI command.
bit 4
DD
DD
threshold for a time > 100 μs (typ) is a wake-up event
DD
over-current has no effect
over-current has no effect
DD
current monitoring functionality. V
POR
, while V
WD_spi[1]
SUP-TH1
bit 3
0
SUP1
), and device in Reset mode
is falling toward GND
SUP_TH1
Analog Integrated Circuit Device Data
WD_spi[0]
bit 2
0
)
DD_OC_LP
Freescale Semiconductor
WD N/Win
bit 1
1
DD
threshold is defined in
current > V
Crank
DD_OC_LP
bit 0
0