MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 72

• Manufacturer Part Number: MCZ33905S5EK
• Description: IC SYSTEM BASIS CHIP GEN2 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905S5EK

• Applications: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

allow to decode the device current mode.
REGULATOR, CAN, I/O, INT AND LIN REGISTERS
72
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 31. REGULATOR Register, REG
Tables below describe the meaning of MISO bits 7-0, that
Table 29. MISO bits 7-3
[b_15 b_14] 01_111 [P/N]
b7 b6
b4 b3
MOSI First Byte [15-8]
Bits
Condition for default
00
01
10
11
00
01
10
11
b2
b1
b0
0
1
0
1
01 01_ 111 P
Default state
Device current mode, any of the above command
b7, b6, b5, b4, b3
0 0000
0 0001
0 0010
0 0011
V
Regulator OFF
Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags not reported. V
detected after 1.0 ms blanking time.
Regulator ON. Under-voltage (UV) and over-current (OC) monitoring flags active. V
after 1.0 ms blanking time.
Regulator ON. Under-voltage (UV) and over-current (OC) monitoring flags active. V
after 25 μs blanking time.
5 V-can[1], 5 V-can[0] - 5V-CAN regulator control
Regulator OFF
Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags not reported. 1.0 ms
blanking time for UV and OC detection.
Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags active. 1.0 ms blanking
time for UV and OC detection.
Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags active. 5 V-CAN disable
in case UV or OC detected after 25 μs blanking time.
V
External V
External V
V
Disable the automatic activation of the external ballast
Enable the automatic activation of the external ballast, if V
V
AUX
DD
DD
DD
bal en - Control bit to Enable the V
bal auto - Control bit to automatically Enable the V
OFF en - Control bit to allow transition into Low Power V
[1], V
DD
DD
AUX
ballast disable
ballast Enable
[0] - Vauxilary regulator control
V
bit 7
AUX
0
[1]
POR
Normal Request
Normal mode
FLASH
MODE
V
INIT
AUX
bit 6
0
[0]
DD
external ballast transistor
bit 5
N/A
-
DD
Description
5V-can[1]
MOSI Second Byte, bits 7-0
DD
bit 4
decoding.
external ballast transistor, if V
0
DD
> typ 60 mA
Table below describes the SAFE and DEBUG bit
Table 30. SAFE and DEBUG status
OFF mode (to prevent V
POR
5V-can[0]
b1
b0
0
1
0
1
bit 3
0
SAFE and DEBUG bits
AUX
AUX
Analog Integrated Circuit Device Data
V
DD
is disabled in case UV or OC detected
is disabled in case UV or OC detected
bit 2
N/A
SAFE pin ON, driver activated.
DD
bal en
DD
SAFE pin OFF, not activated
AUX
is > typ 60 mA
turn OFF)
Debug mode Active
Debug mode OFF
is disabled in case UV or OC
description
description
Freescale Semiconductor
V
DD
bit 1
N/A
bal auto
V
DD
bit 0
N/A
OFF en