MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 66

• Manufacturer Part Number: MCZ33905S5EK
• Description: IC SYSTEM BASIS CHIP GEN2 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905S5EK

• Applications: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 18. Initialization Miscellaneous Functions, INIT MISC (Note: Register can be written only in INIT mode)
Notes
26.
b2, b1, b0
[b_15 b_14] 0_1000 [P/N]
MOSI First Byte [15-8]
100
101
110
111
Bit
0xx
Condition for default
b7
b6
b5
b4
b3
0
1
0
1
0
1
0
1
Bits b2,1 and 0 allow the following operation:
First, check the resistor device has detected at the DEBUG pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt
register (ref to device flag table).
Second, over write the resistor decoded by device, to set the SAFE mode operation by SPI. Once this function is selected by bit 2 = 1,
this selection has higher priority than “hardware”, and device will behave according to b2,b1 and b0 setting
01 01_ 000 P
Default state
LPM w RNDM - This enables the usage of random bits 2, 1 and 0 of the MODE register to enter into Low Power VDD OFF or Low Power VDD ON.
Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG pin. Ref to parametric table for resistor range
LPM w RNDM
Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in flash mode.
bit 7
0
100 verification enable: resistor at DBG pin is typ 68 kohm (RB3) - Selection of SAFE mode B3
110 verification enable: resistor at DBG pin is typ 15 kohm (RB1) - Selection of SAFE mode B1
101 verification enable: resistor at DBG pin is typ 33 kohm (RB2 - Selection of SAFE mode B2
111 verification enable: resistor at DBG pin is typ 0 kohm (RA) - Selection of SAFE mode A
Function disable: the Low Power mode can be entered without usage of Random Code
INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode
INT pulse duration is typ 100 μs. Ref to dynamic parameter table for exact value.
Function disable: the parity is not used. The parity bit must always set to logic 0.
INT pulse duration is typ 25 μs. Ref to dynamic parameter table for exact value.
Function enabled: the Low Power mode is entered using the Random Code
SPI parity
bit 6
Function enable: the parity is used, and parity must be calculated.
0
INT pulse -Select INT pin operation: low level pulse or low level
INT pin will assert a low level pulse, duration selected by bit [b4]
SPI parity - Select usage of the parity bit in SPI write operation
INT pin assert a permanent low level (no pulse)
INT pulse
INT width - Select the INT pulse duration
bit 5
0
Function disable
Function disable
Description
INT width
MOSI Second Byte, bits 7-0
value.
bit 4
(26)
POR
INT flash
bit 3
0
Analog Integrated Circuit Device Data
Dbg Res[2]
bit 2
0
Freescale Semiconductor
Dbg Res[1]
bit 1
0
Dbg Res[0]
bit 0
0