MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 32

• Manufacturer Part Number: MCZ33905S5EK
• Description: IC SYSTEM BASIS CHIP GEN2 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905S5EK

• Applications: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DGB (DGB) AND DEBUG MODE
The DBG pin has 2 functions:
Primary function:
achieved by applying a voltage between 8.0 and 10 V, at the
DEBUG pin, and then powering up the device (ref to state
diagram). When device leaves the INIT reset mode and enter
in INIT mode, device detects that voltage at DEBUG pin is
within the 8.0 to 10 V range, and activate the debug mode.
commands is necessary. This allow easy debug of the
hardware and software routines (i.e SPI commands).
debug mode, when voltage at DBG pin falls below the 8.0 to
10 V range, the debug mode is left, and device start W/D
operation, and expect proper W/D refresh. Debug mode can
be left by SPI. Such command is recommended to avoid
staying in debug mode in case of unwanted debug mode
selection (FMEA pin). SPI command to leave debug has
higher priority than providing 8.0 to 10 V at the DEBUG pin.
Secondary function:
selects the Fail Safe mode operation. DBG pin can also be
connected directly to GND (this prevent usage of debug
mode).
32
33903/4/5
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
V
It is an input used to set the device in Debug mode. This is
When debug mode is detected, no watchdog SPI refresh
Device is in debug mode is reported by SPI flag. While in
The resistor connected between DBG pin and GND
BAT
R
SENSE
VSENSE
VSUP_1
1.0 k
D1
I/O-0
I/O-1
S_I/O_att
S_in
S_in
S_in
S_in
S_I/O_att
Figure 19. Analog Multiplexer Block Diagram
Multiplexer
Temp
V
REF
5 V-CAN
buffer
: 2.5 V
S_iddc
S_g3.3
operation via a resistor at the DBG pin or via a SPI command.
The SPI command has higher priority than the hardware
selection via Debug resistor.
not be configured via the resistor connected at DBG pin.
SAFE
Safe output pin
event occurs. The objective is to drive electrical safe circuitry
and set the ECU in a know sate independent of the MCU and
SBC, once a failure has been detected.
up.
INTERRUPT (INT)
when an interrupt condition occurs. The INT condition is
enabled in the INT register. The selection of low level or pulse
as well as pulse duration are selected by SPI.
low, in Low Power V
connection of an external pull-up resistor, and connection of
an INT pin from other ICs without extra consumption in
unpowered mode.
Flexibility is provided to the user to select SAFE output
When the Debug mode is selected, the SAFE modes can
This pin is an output which is asserted low in case a fault
The SAFE output structure is an open drain, without a pull-
The INT output is asserted low or generate a low pulse
No current will flow inside the INT structure when V
All swicthes and resistor are configured and controlled via the SPI
R
S_g3.3 and S_g5 for 5.0 V or 3.3 V VDD versions
S_iddc to select V
S_in1 for Low Power mode resistor bridge disconnection
S_ir to switch on/off of the internal R
S_I/O_att for I/O-0 and I/O-1 attenuation selection
M
S_g5
: internal resistor connected when V
V
DD-I_COPY
R
S_ir
DD
DD
MI
Analog Integrated Circuit Device Data
regulator current copy
OFF mode. This allows the
5 V-CAN
MUX-OUT
R
M(*)
MI
Freescale Semiconductor
resistor
REG
current monitor is used
(*)Optional
MCU
A/D in
DD
is