MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 48

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MCZ33905S5EK

Manufacturer Part Number
MCZ33905S5EK
Description
IC SYSTEM BASIS CHIP GEN2 32SOIC
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MCZ33905S5EK

Applications
System Basis Chip
Interface
CAN, LIN
Voltage - Supply
5.5 V ~ 27 V
Package / Case
32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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SAFE mode B1, B2 and B3 illustration:
resistor or SPI configuration.
48
33903/4/5
FAIL SAFE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
Figure 29
step 1: Failure illustration
GND
enter in SAFE mode to evaluate resistor at DBG pin
SAFE
V
100 ms delay time to enter in SAFE mode
step 2:
Exclusive detection of
ECU external event to
R
SPI configuration
disable V
SAFE
and monitor ECU external events
RST
V
SAFE
illustrates the event, and consequences when SAFE mode B1, B2, or B3 is selected via the appropriate debug
V
DD
RST
RST
DD
DBG
DD
8 x 256 ms delay time to enter in SAFE mode
100 ms deglitcher time to activate SAFE and
failure event, i.e W/D
resistor or
OFF state ON state
to evaluate resistor at DBG pin
OFF state ON state
OFF state
failure event, V
failure event, Reset s/c GND
DD
to evaluate resistor at the DBG pin
and monitor ECU external events
and monitor ECU external events
based on
1st
V
2.5 V
DD_UV TH
Behavior illustration for the safe state B (R
DD
100 ms
Figure 29. SAFE Modes B1, B2, or B3 Behavior Illustration
low
2nd
100 ms
DBG resistor => safe state B1
DBG resistor => safe state B2
DBG resistor => safe state B3
ON state
CAN bus
CAN bus
I/O-1
8th
I/O-1
step 3: Consequences for V
GND
V
SAFE
SAFE
SAFE
V
V
DD
RST
RST
RST
DD
DD
CAN bus idle time
I/O-1 high to low transition
I/O-1 high to low transition
CAN bus idle time
V
DD
< V
DD_UV TH
DG
> 10 kohm)
DD
Analog Integrated Circuit Device Data
If Reset s/c GND recovered
V
DD
If V
OFF
DD
V
failure recovered
DD
Freescale Semiconductor
OFF

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