MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 59

• Manufacturer Part Number: MCZ33905S5EK
• Description: IC SYSTEM BASIS CHIP GEN2 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905S5EK

• Applications: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

COMPLETE SPI OPERATION
options. Both MOSI and MISO information are described.
is selected and parity = 1.
PARITY BIT 8
Calculation
15,14 = 01). It is calculated based on the number of logic one
Table 11. Device Registers with Corresponding Address
Table 12. SPI Capabilities with Options
Analog Integrated Circuit Device Data
Freescale Semiconductor
Read back of “device control bits” (MOSI bit 7 = 0)
Write device control bit to address selected by bits
register address (bit 13-9), and sub address (bit 7).
Read specific device information (MOSI bit 7 = 1)
MISO return fixed device status (bit 15-8) + flags
from the selected address and sub-address.
Table 12
Read device flags and wake-up flags, from
Note:
The parity is used for write to register command (bit
0_1010
0_1011
0_1100
0_1101
0_1110
0_1111
1_0000
1_0001
1_0010
1_0011
1_0100
MISO return 16 bits device status
P = 0 if parity bit is not selected or parity = 0. P = 1 if parity
Type of Command
is a compiled view of all the SPI capabilities and
Reserved
(13-9).
Timer_A: W/D & Low Power MCU consumption
Timer_C: W/D Low Power & Forced Wake-up
OR
Timer_B: Cyclic Sense & Cyclic Interrupt
CAN interface control
LIN2 interface control
LIN1 interface control
Input Output control
Watchdog Refresh
Regulator Control
Interrupt Control
Mode register
MOSI/
MISO
MOSI
MISO
MOSI
MISO
MOSI
MISO
MOSI
MISO
MISO
MOSI
MISO
MOSI
Control bits
[15-14]
00
00
01
10
11
11
Device Fixed Status (8 bits)
Device Fixed Status (8 bits)
Device Fixed Status (8 bits)
Device Fixed Status (8 bits)
Device Fixed Status (8 bits)
Interrupt
TIM_A
TIM_B
TIM_C
MODE
REG
W/D
CAN
LIN1
LIN2
I/O
Address
address
address
address
address
address
[13-9]
contained in bits 15-9,7-0 sequence (this is the whole 16 bits
of the write command except bit 8).
Examples 1:
because the command contains 7 bits with logic 1.
Bit 8 must be set to 0 if the number of 1 is odd.
Bit 8 must be set to 1if the number of 1 is even.
MOSI [bit 15-0] = 01 00 011 P 01101001, P should be 0,
Thus the Exact command will then be:
MOSI [bit 15-0] = 01 00 011 0 01101001
1) Write to register to select Low Power mode, with optional “Inverted
1) Write “device control bits” to register address, to select device
Parity/Next
Reserved
bits [8]
3) Read device flags from each of the register addresses.
(note)
1
1
1
Random code” and select wake-up functionality
1) Write “timing values” to register address.
2) Read back register “timing values”
Reserved
2) Read back register “control bits”.
Read back device “Current mode”
Bit 7
Watchdog Refresh Commands
0
1
0
1
Read “Random Code”,
Leave “Debug mode”
2) Read operations:
Reserved
Read of device flags form a register address,
Read of device flags form a register address,
Device Extended Status (8 bits)
SERIAL PERIPHERAL INTERFACE
operation.
Register control bits content
Device ID and I/Os state
and sub address HIGH (bit 7)
and sub address LOW (bit 7)
Control bits
Flags
Flags
Bits [6-0]
000 0000
000 0000
DETAIL OPERATION
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