MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 50

• Manufacturer Part Number: MCZ33905S5EK
• Description: IC SYSTEM BASIS CHIP GEN2 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905S5EK

• Applications: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

two states: recessive or dominant. The driver state is
controlled by the TXD pin. The bus state is reported through
the RXD pin.
and CANH and CANL lines are biased to the voltage set with
5 V-CAN divided by 2, or approx. 2.5 V.
and CANL and CANH drivers are active. CANL is pulled low
and CANH is pulled high.
voltage is compared versus an internal threshold (a few
hundred mV).
recessive and RXD is set high.
dominant and RXD is set low.
SPLIT output.
TxD/RxD Mode and Slew Rate Selection
default and if no SPI is used, the device is in the fastest slew
rate. Three slew rates are available. The slew rate controls
the recessive to dominant, and dominant to recessive
transitions. This also affects the delay time from the TXD pin
.
Wake-up
enabled, the CAN bus traffic is detected. The CAN bus wake-
50
33903/4/5
CAN INTERFACE
CAN INTERFACE DESCRIPTION
When the CAN interface is in Normal mode, the driver has
When TXD is high, the driver is set in the recessive state,
When TXD is low, the bus is set into the dominant state,
The RXD pin reports the bus state: CANH minus the CANL
If “CANH minus CANL” is below the threshold, the bus is
If “CANH minus CANL” is above the threshold, the bus is
The SPLIT pin is active and provide a 2.5 V biasing to the
The CAN signal slew rate selection is done via the SPI. By
When the CAN interface is in Sleep mode with wake-up
SPLIT
2.5 V
TXD
2.5 V
CANL
CANH
RXD
Bus Driver
Dominant state
CANH-DOM
CANL-DOM
CANH-CANL
Normal or Listen Only mode
Recessive state
CANL/CANH-REC
Figure 31. Bus Signal in TxD/RxD and Low Power Mode
(bus dominant set by other IC)
Receiver
to the bus, and from the bus to the RXD. The loop time is thus
affected by the slew rate selection.
Minimum Baud rate
permanent dominant timing detection. The maximum number
of consecutive dominant bits in a frame is 12 (6 bits of active
error flag and its echo error flag).
to a single bit time of: 300 μs / 12 = 25 μs.
SLEEP MODE
CANH and CANL driver are disabled and CANH and CANL
lines are terminated to GND via the R
pin is high-impedance. In order to monitor bus activities, the
CAN wake-up receiver can be enabled. It is supplied
internally from V
reporting by dedicated flags in SPI and by INT pulse, and
results in a device wake-up if device was in Low Power mode.
CANL are set back into the recessive level. This is illustrated
in
up is a pattern wake-up. The wake-up by the CAN is enabled
or disabled via the SPI.
Figure
The minimum baud is determined by the shortest TXD
The shortest TXD dominant detection time of 300 μs lead
So the minimum Baud rate is 1 / 25 μs = 40 kBaud.
Sleep mode is a reduced current consumption mode.
Wake-up events occurring on the CAN bus pin are
When the device is set back into Normal mode, CANH and
31.
High ohmic termination (50 kohm) to GND
SUP2
Sleep or Stand-by mode
Go to sleep,
High-impedance
.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Normal or Listen Only mode
IN
resistor, the SPLIT