MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 71

• Manufacturer Part Number: MCZ33905S5EK
• Description: IC SYSTEM BASIS CHIP GEN2 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905S5EK

• Applications: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

flags must be cleared or read.
37, Device Flag, I/O Real Time and Device
the selected low power mode and immediately wake up. In
addition, the CAN failure flags (i.e CAN_F and CAN_UF)
must be cleared in order to meet the low power current
consumption specification. This is done by the following SPI
command:
SPI command uses a write to “Normal Request mode”,
0x5C10.
Mode Register Features
SPI command” that allow the following:
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 28. Device Modes
Prior to enter in LP V
This is done by the following SPI commands (See
0xE100 for CAN wake up clear
0xE380 for I/O wake up clear
0xE700 for LIN1 wake up clear
0xE900 for LIN2 wake up clear
If wake-up flags are not cleared, the device will enter into
0xE180 (read CAN failure flags)
When the device is in LP V
The mode register include specific function and “global
- read device current mode
- read device Debug status
- read state of SAFE pin
Read device current mode, Leave debug mode.
Read device current mode, Leave debug mode.
Read device current mode, Keep DEBUG mode
MISO reports Debug and SAFE state (bits 1,0)
MISO reports Debug and SAFE state (bits 1,0)
Global commands and effects
Release SAFE pin (turn OFF).
Release SAFE pin (turn OFF).
MOSI in hexadecimal: DD 00
MOSI in hexadecimal: DD 80
MOSI in hexadecimal: 1D 00
MOSI in hexadecimal: 1D 80
Read device current mode
Keep SAFE pin as is.
Keep SAFE pin as is.
DD
ON or LP V
DD
ON mode, the wake-up by a
DD
OFF, the wake-up
Identification):
MOSI
MISO
MOSI
MISO
MOSI
MISO
MOSI
MISO
Table
bits 15-14
bits 15-14
bits 15-14
bits 15-14
00
00
11
11
Fix Status
Fix Status
Fix Status
Fix Status
bit 15-8
bit 15-8
bit 15-8
bit 15-8
adress bit [13-9], along with several combinations of bit [15-
14] and bit [7]. Note, bit [8] is always set to 1.
Entering into LP Mode using Random Code
mode via bit 7 of the INIT MISC register.
0x1D80 command. The 3 Random Code bits are available on
MISO bits 2,1 and 0.
FWU:
Rnd_[0].
bits 13-9
bits 13-9
bits 13-9
bits 13-9
01 110
01 110
01 110
01 110
1. in hex: 0x5C60 to enter in LP VDD OFF mode without
2. if Random Code is selected, the commands are:
- leave Debug state
- release or turn off SAFE pin
- read a 3 bit Random Code to enter in LP mode
These global commands are built using the MODE register
- LP Mode using Random Code must be selected in INIT
- In Normal Mode, read the Random Code using 0x1D00 or
- Write LP Mode by inverting the 3 random bits.
Example - Select LP VDD OFF without cyclic sense and
- Read Random Code: 0x1D00 or 0x1D80,
MISO report in binary: bits 15-8, bits 7-3, Rnd_[2], Rnd_[1],
- Write LP VDD OFF Mode, using Random Code inverted:
in binary: 0101 1100 0110 0 Rnd_b[2], Rnd_b[1], Rnd_b[0].
Table 28
using the 3 random code bits.
DETAIL OF CONTROL BITS AND REGISTER MAPPING
device current mode
device current mode
device current mode
device current mode
summarizes these commands
bit 8
bit 8
bit 8
bit 8
1
1
1
1
bit 7-3
bit 7-3
bit 7-3
bit 7-3
bit 7
bit 7
bit 7
bit 7
0
1
0
1
SERIAL PERIPHERAL INTERFACE
bit 2
bit 2
X
X
Random code
Random code
000 0000
000 0000
000 0000
000 0000
bits 6-0
bits 6-0
bits 6-0
bits 6-0
SAFE
SAFE
bit 2-0
bit 2-0
bit 1
bit 1
DEBUG
DEBUG
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bit 0
bit 0
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