MCZ33905S5EK Freescale Semiconductor, MCZ33905S5EK Datasheet - Page 57

• Manufacturer Part Number: MCZ33905S5EK
• Description: IC SYSTEM BASIS CHIP GEN2 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905S5EK

• Applications: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

arrangement:
Analog Integrated Circuit Device Data
Freescale Semiconductor
The device is using a 16 bits SPI, with the following
MOSI, Master Out Slave In bits:
• bits 15 and 14 (called C1 and C0) are control bits to
• bit 13 to 9 (A4 to A0) to select the register address.
• bit 8 (P/N) has two functions: parity bit in write mode
MISO
MOSI
SCLK
MOSI
MISO
select the SPI operation mode (write control bit to
device register, read back of the control bits, read of
device flag).
(optional, = 0 if not used), Next bit ( = 1) in read mode.
CS
Bit 15
Tri-state
control bits
S15
C1
Don’t ca
Bit 14
S14
C0
Bit 13
S13
A4
S15
C1
Device Status
Bit 12
S12
register address
A3
C0
S14
Bit 11
S11
A2
SERIAL PERIPHERAL INTERFACE
Bit 10
S10
A1
SPI Wave Form, and Signals Polarity
D0
Bit 9 Bit 8
Do0
Figure 38. Device SPI Overview
S9
A0
HIGH LEVEL OVERVIEW
Parity (optional) or
Next bit = 1
P/N
S8
Don’t ca
Tri-state
CS active low. Must rise at end of 16 clocks,
SCLK signal is low outside of CS active
for write commands, MOSI bits [15, 14] =  [0 1]
Extended Device Status, Register Control bits or Device Flags
Bit 7
capability.
Do7
D7
• bit7 to 0 (D7 to D0): control bits
MISO, Master IN Slave Out bits:
• bits 15 to 8 (S15 to S8) are device status bits
• bits 7 to 0 (Do7 to Do0) are either extended device
The SPI implementation does not support daisy chain
Figure 38
MISO tri-state outside of CS active
MOSI and MISO data changed at SCLK rising edge
and sampled at falling edge. Msb first.
status bits, device internal control register content or
device flags.
Bit 6
D6
Do6
Bit 5
Do5
D5
is an overview of the SPI implementation.
D4
Do4
Bit 4
data
Bit 3
D3
Do3
SERIAL PERIPHERAL INTERFACE
Bit 2
D2
Do2
Bit 1 Bit 0
D1
Do1
HIGH LEVEL OVERVIEW
Do0
D0
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