ISP1761ET

Manufacturer Part NumberISP1761ET
DescriptionUSB Interface IC USB 2.0 HS OTG HOST
ManufacturerNXP Semiconductors
ISP1761ET datasheet
 


Specifications of ISP1761ET

Operating Supply Voltage1.65 V to 3.6 VLead Free Status / Rohs Status Details
Other namesISP1761ET,557  
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ISP1761
Hi-Speed Universal Serial Bus On-The-Go controller
Rev. 04 — 5 March 2007
1. General description
The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)
Controller integrated with advanced NXP slave Host Controller and the NXP ISP1582
Peripheral Controller.
The Hi-Speed USB Host Controller and Peripheral Controller comply to
Serial Bus Specification Rev. 2.0”
The Enhanced Host Controller Interface (EHCI) core implemented in the Host Controller is
adapted from
Bus Rev.
Specification Rev.
The ISP1761 has three USB ports. Port 1 can be configured to function as a downstream
port, an upstream port or an OTG port; ports 2 and 3 are always configured as
downstream ports. The OTG port can switch its role from host to peripheral, and
peripheral to host. The OTG port can become a host through the Host Negotiation
Protocol (HNP) as specified in the OTG supplement.
2. Features
I
Compliant with
transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
I
Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)
peripheral support
I
Three USB ports that support three operational modes:
N
Mode 1: Port 1 is an OTG Controller port, and ports 2 and 3 are Host Controller
ports
N
Mode 2: Ports 1, 2 and 3 are Host Controller ports
N
Mode 3: Port 1 is a Peripheral Controller port, and ports 2 and 3 are Host Controller
ports
I
Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
I
Multitasking support with virtual segmentation feature (up to four banks)
I
High-speed memory controller (variable latency and SRAM external interface)
I
Directly addressable memory architecture
I
Generic processor interface to most CPUs, such as Hitachi SH-3 and SH-4, NXP XA,
Intel StrongARM, NEC and Toshiba MIPS, Freescale DragonBall and PowerPC
Reduced Instruction Set Computer (RISC) processors
I
Configurable 32-bit and 16-bit external memory data bus
I
Supports Programmed I/O (PIO) and Direct Memory Access (DMA)
I
Slave DMA implementation on CPU interface to reduce the host system’s CPU load
and support data transfer speeds of up to 480 Mbit/s.
Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial
1.0”. The OTG Controller adheres to
1.2”.
Ref. 1 “Universal Serial Bus Specification Rev.
Product data sheet
Ref. 1 “Universal
Ref. 3 “On-The-Go Supplement to the USB
2.0”; supporting data

ISP1761ET Summary of contents

  • Page 1

    ISP1761 Hi-Speed Universal Serial Bus On-The-Go controller Rev. 04 — 5 March 2007 1. General description The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) Controller integrated with advanced NXP slave Host Controller and the NXP ISP1582 ...

  • Page 2

    ... NXP Semiconductors I Separate IRQ, DREQ and DACK lines for the Host Controller and the Peripheral Controller I Integrated multi-configuration FIFO I Double-buffering scheme increases throughput and facilitates real-time data transfer I Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI I Tolerant I/O for low voltage CPU interface (1. 3 ...

  • Page 3

    ... NXP Semiconductors N Slave DMA, fully autonomous and supports multiple configurations N Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT endpoint N Integrated 8 kB memory N Software-controllable connection to the USB bus, SoftConnect 3. Applications The ISP1761 can be used to implement a dual-role USB device in any application, USB host or USB peripheral, depending on the cable connection ...

  • Page 4

    ... Type number Package Name Description ISP1761BE LQFP128 plastic low profile quad flat package; 128 leads; body 14 ISP1761ET TFBGA128 plastic thin fine-pitch ball grid array package; 128 balls; body 9 ISP1761_4 Product data sheet Rev. 04 — 5 March 2007 ISP1761 Hi-Speed USB OTG controller ...

  • Page 5

    ... NXP Semiconductors 5. Block diagram 47, 49, 51, 52 78, 80 D[15:0]/D[31:0] 82, 84, 86, 87 98, 100 to 103, 105 17 A[17:1] CS_N 106 RD_N 107 WR_N 108 DC_IRQ 111 HC_IRQ 112 DC_DREQ 113 HC_DREQ 114 HC_DACK 116 DC_DACK 117 124 C_B ...

  • Page 6

    ... Fig 2. Pin configuration (LQFP128); top view Fig 3. Pin configuration (TFBGA128); top view ISP1761_4 Product data sheet 1 ISP1761BE 38 ball A1 index area ISP1761ET Rev. 04 — 5 March 2007 ISP1761 Hi-Speed USB OTG controller 102 65 004aaa506 004aaa551 © NXP B.V. 2007. All rights reserved 163 ...

  • Page 7

    ... NXP Semiconductors 6.2 Pin description Table 2. Pin description [1][2] Symbol Pin Ball LQFP128 TFBGA128 OC3_N 1 C2 REF5V GNDA 4 A1 REG1V8 CC(5V0 CC(5V0) GND(OSC REG3V3 CC(I/O) XTAL1 11 E1 XTAL2 12 F2 CLKIN 13 F1 GNDD 14 G3 GND(RREF1 RREF1 16 G1 [4] GNDA 17 H2 DM1 18 H1 GNDA ...

  • Page 8

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Ball LQFP128 TFBGA128 PSW2_N 28 M1 GND(RREF3 RREF3 30 N1 [6] GNDA 31 P2 DM3 32 P1 GNDA 33 R2 DP3 34 R1 PSW3_N 35 T1 GNDD 36 T2 DATA0 37 R3 DATA1 38 T3 DATA2 CC(I/O) DATA3 41 P5 DATA4 42 T5 DATA5 43 R5 ...

  • Page 9

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Ball LQFP128 TFBGA128 DATA9 49 T8 REG1V8 50 R8 DATA10 51 P9 DATA11 52 T9 GNDC 53 R9 DATA12 54 T10 GNDD 55 R10 DATA13 56 P11 DATA14 57 T11 DATA15 58 R11 V 59 T12 CC(I/O) DATA16 60 R12 DATA17 61 T13 DATA18 62 R13 ...

  • Page 10

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Ball LQFP128 TFBGA128 DATA21 66 R15 V 67 P15 CC(I/O) DATA22 68 T16 DATA23 69 R16 DATA24 70 P16 GNDD 71 N16 DATA25 72 N15 DATA26 73 M15 DATA27 74 M16 V 75 M14 CC(I/O) DATA28 76 L16 DATA29 77 L15 DATA30 78 K16 GNDD ...

  • Page 11

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Ball LQFP128 TFBGA128 A2 84 H15 REG1V8 85 G16 A3 86 H14 A4 87 F16 GNDC 88 G15 A5 89 F15 GNDD 90 E16 A6 91 F14 A7 92 E15 A8 93 D16 V 94 D15 CC(I/ C16 A10 96 C15 A11 97 B16 A12 ...

  • Page 12

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Ball LQFP128 TFBGA128 CS_N 106 A12 RD_N 107 B12 WR_N 108 B11 GNDD 109 A11 BAT_ON_N 110 C10 DC_IRQ 111 A10 HC_IRQ 112 B10 DC_DREQ 113 A9 HC_DREQ 114 B9 V 115 C8 CC(I/O) HC_DACK ...

  • Page 13

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Ball LQFP128 TFBGA128 RESET_N 122 B6 GNDA 123 B5 C_B 124 A5 C_A 125 B4 V 126 A4 CC(C_IN) OC1_N/V 127 B3 BUS OC2_N 128 A3 [1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals. ...

  • Page 14

    ... NXP Semiconductors 7. Functional description 7.1 ISP1761 internal architecture: advanced NXP slave Host Controller and hub The EHCI block and the Hi-Speed USB hub block are the main components of the advanced NXP slave Host Controller. The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the ISP1761 is adapted from Universal Serial Bus Rev ...

  • Page 15

    ... NXP Semiconductors Fig 4. Internal hub 7.1.1 Internal clock scheme and port selection Figure 5 Fig 5. ISP1761 clock scheme ISP1761_4 Product data sheet EHCI ROOT HUB PORTSC1 ENUMERATION AND POLLING USING ACTUAL PTDs INTERNAL HUB (TT) PORT2 PORT1 shows the internal clock scheme of the ISP1761. The ISP1761 has three ports. ...

  • Page 16

    ... NXP Semiconductors Port 2 does not need to be enabled using software if only port 1 or port 3 is used. No port needs to be disabled by external pull-up resistors, if not used. The DP and DM of the unused ports need not be externally pulled HIGH because there are internal pull-down resistors on each port that are enabled by default ...

  • Page 17

    ... NXP Semiconductors The total amount of memory allocated to the payload determines the maximum transfer size specifi PTD, a larger internal memory size results in less CPU interruption for transfer programming. This means less time spent in context switching, resulting in better CPU usage. A larger buffer also implies that a larger amount of data can be transferred. This transfer, however, can be done over a longer period of time, to maintain the overall system performance ...

  • Page 18

    ... NXP Semiconductors The RAM is structured in blocks of PTDs and payloads so that while the USB is executing on an active transfer-based PTD, the processor can simultaneously fill up another block area in the RAM. A PTD and its payload can then be updated on-the-fly without stopping or delaying any other USB transaction or corrupting the RAM data. ...

  • Page 19

    ... NXP Semiconductors 63 kB USB HIGH-SPEED USB BUS HOST AND TRANSACTION TRANSLATOR (FULL-SPEED AND LOW-SPEED) Fig 6. Memory segmentation and access block diagram Both the CPU interface logic and the USB Host Controller require access to the internal ISP1761 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 MB/s ...

  • Page 20

    ... NXP Semiconductors register access must always be completed using two subsequent accesses. In the case of a DMA transfer, the 16-bit or 32-bit data bus width configuration will determine the number of bursts that will complete a certain transfer length. In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA mode, the data validation is performed by DACK, instead of CS_N, together with the WR_N and RD_N signals ...

  • Page 21

    ... NXP Semiconductors 7.3.3 PIO mode access, register read cycle The PIO register read access is similar to a general register access not necessary to set a pre-fetching address before a register read. The ISP1761 register read address will not automatically be incremented during consecutive read accesses, unlike in a series of ISP1761 memory read cycles. The ISP1761 register read address must be correctly specifi ...

  • Page 22

    ... NXP Semiconductors It is also possible that the system’s DMA will perform a memory-to-memory type of transfer between the system memory and the ISP1761 memory. The ISP1761 will be accessed in PIO mode. Consequently, memory read operations must be preceded by initializing the Memory register (address 033Ch), as described in will be generated by the ISP1761 on completing the DMA transfer but an internal processor interrupt may be generated to signal that the DMA transfer is completed ...

  • Page 23

    ... NXP Semiconductors 3. Define the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW Mode Control register. These settings must match IRQ settings of the host processor. By default, interrupt is level-triggered and active LOW. 4. Program the individual Interrupt Enable bits in the HcInterruptEnable register. The software will need to clear the Interrupt Status bits in the HcInterrupt register before enabling individual interrupt enable bits ...

  • Page 24

    ... NXP Semiconductors With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer (ISO, INT and bulk), software can determine which PTDs get priority and an interrupt will be generated when the AND or OR conditions are met. The PTDs that are set will wait until the respective bits of the remaining PTDs are set and then all PTDs generate an interrupt request to the CPU together ...

  • Page 25

    ... NXP Semiconductors The PLL block generates all the main internal clocks required for normal functionality of various blocks: 30 MHz, 48 MHz and 60 MHz. No external components are required for the PLL operation. 7.6 Power management The ISP1761 implements a flexible power management scheme, allowing various power saving stages ...

  • Page 26

    ... NXP Semiconductors count, the ISP1761 will switch back to suspend mode after the specified time. The maximum delay that can be programmed in the clock-off count field is approximately 500 ms. Additionally, the Power Down Control register allows ISP1761 internal blocks to disable for lower power consumption as defined in The lowest suspend current, I room temperature ...

  • Page 27

    ... NXP Semiconductors Fig 7. ISP1761 power supply connection Figure 8 ISP1761_4 Product data sheet V CC(5V0 10, 40, 48, CC(I/O) 59, 67, 75, 83, 94, 104, 115 REG1V8 85 ISP1761BE REG1V8 5, 50, 118 REG3V3 9 V CC(C_IN) 126 The figure shows the LQFP pinout. For the TFBGA ballout, see A 4.7 F-to-10 F electrolytic or tantalum capacitor is required on any one of the pins 5, 50 and 118 ...

  • Page 28

    ... NXP Semiconductors Fig 8. Most commonly used power supply connection 7.7.1 Hybrid mode Table 6 Table 6. Voltage V CC(5V0) V CC(I/O) In hybrid mode (see transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the suspend current CC(5V0) back on, before the resume programming sequence starts. ...

  • Page 29

    ... NXP Semiconductors Fig 9. Hybrid mode Table 7 Table 7. Pins DATA[31:0], A[17:1], TEST, HC_IRQ, DC_IRQ, HC_DREQ, DC_DREQ, HC_DACK, DC_DACK, HC_SUSPEND/WAKEUP_N, DC_SUSPEND/WAKEUP_N CS_N, RESET_N, RD_N, WR_N 7.8 Overcurrent detection The ISP1761 can implement a digital or analog overcurrent detection scheme. Bit 15 of the HW Mode Control register can be programmed to select the analog or digital overcurrent detection ...

  • Page 30

    ... NXP Semiconductors For an overcurrent limit of 500 mA per port, a PMOS transistor with R approximately 100 m is required PMOS transistor with a lower R analog overcurrent detection can be adjusted using a series resistor; see V PMOS V PMOS I OC(nom) (1) R Fig 10. Adjusting analog overcurrent detection limit (optional) The digital overcurrent scheme requires using an external power switch with integrated overcurrent detection, such as LM3526, MIC2526 (2 ports) or LM3544 (4 ports) ...

  • Page 31

    ... NXP Semiconductors The internal POR pulse will be generated whenever V than 11 s. (1) PORP = Power-On Reset Pulse. Fig 11. Internal power-on reset timing The recommended RESET input pulse length at power-on must be at least ensure that internal clocks are stable. The RESET_N pin can be either connected to V externally controlled by the microcontroller, ASIC, and so on ...

  • Page 32

    ... NXP Semiconductors 8. Host Controller Table 8 • All registers range from 0000h to 03FFh. These registers can be read or written as double word, that is 32-bit data. • Operational registers range from 0000h to 01FFh. Host Controller-specific and OTG Controller-specific registers range from 0300h to 03FFh. Peripheral Controller-specific registers range from 0200h to 02FFh. • ...

  • Page 33

    ... NXP Semiconductors Table 8. Address 033Ch 0340h 0344h 0354h Interrupt registers 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch 8.1 EHCI capability registers 8.1.1 CAPLENGTH register The bit description of the Capability Length (CAPLENGTH) register is given in Table 9. CAPLENGTH - Capability Length register (address 0000h) bit description ...

  • Page 34

    ... NXP Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol PRR Reset 0 Access R Table 12. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. 8.1.4 HCCPARAMS register The Host Controller Capability Parameters (HCCPARAMS) register bytes register, and the bit allocation is given in Table 13 ...

  • Page 35

    ... NXP Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 1 Access R Table 14. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. 8.2 EHCI operational registers 8.2.1 USBCMD register The USB Command (USBCMD) register indicates the command to be executed by the serial Host Controller ...

  • Page 36

    ... NXP Semiconductors Table 15. USBCMD - USB Command register (address 0020h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol LHCR Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...

  • Page 37

    ... NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 18. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. ...

  • Page 38

    ... NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 [1] Symbol reserved Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 20. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. ...

  • Page 39

    ... NXP Semiconductors Table 22. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. 8.2.6 PORTSC1 register The Port Status and Control (PORTSC) register (bit allocation: well reset by hardware only when the auxiliary power is initially applied or in response to a Host Controller reset. The initial conditions of a port are: • ...

  • Page 40

    ... NXP Semiconductors Table 24. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. [2] These fields read logic 0, if the PP (Port Power) bit in register PORTSC 1 is logic 0. 8.2.7 ISO PTD Done Map register The bit description of the register is given in Table 25. ...

  • Page 41

    ... NXP Semiconductors 8.2.8 ISO PTD Skip Map register Table 26 Table 26. ISO PTD Skip Map register (address 0134h) bit description Bit Symbol Access ISO_PTD_SKIP R/W _ MAP[31:0] When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs ...

  • Page 42

    ... NXP Semiconductors Table 29. INT PTD Skip Map register (address 0144h) bit description Bit Symbol Access INT_PTD_SKIP_ R/W MAP[31:0] When a bit in the PTD Skip map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs ...

  • Page 43

    ... NXP Semiconductors When a bit in the PTD Skip map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs. The Skip bit should not normally be set on the position indicated by NextPTDPointer ...

  • Page 44

    ... NXP Semiconductors [1] The reserved bits should always be written with the reset value. Table 35. Bit ISP1761_4 Product data sheet HW Mode Control - Hardware Mode Control register (address 0300h) bit description Symbol Description ALL_ATX_RESET All ATX Reset: For debugging purposes (not used normally). 1 — Enable reset, then write back logic 0 0 — ...

  • Page 45

    ... NXP Semiconductors 8.3.2 HcChipID register Read this register to get the ID of the ISP1761. This upper word of the register contains the hardware version number and the lower word contains the chip ID. bit description of the register. Table 36. HcChipID - Host Controller Chip Identifier register (address 0304h) bit description ...

  • Page 46

    ... NXP Semiconductors Table 39. Bit 8.3.5 HcDMAConfiguration register The bit allocation of the HcDMAConfiguration register is given in Table 40. HcDMAConfiguration - Host Controller Direct Memory Access Configuration register (address 0330h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access ...

  • Page 47

    ... NXP Semiconductors Table 41. Bit DMA_COUNTER[23:0] DMA Counter: The number of bytes to be transferred (read 8.3.6 HcBufferStatus register The HcBufferStatus register is used to indicate the HC that a particular PTD buffer (that is, ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets the Buffer Filled bit of a particular transfer in the HcBufferStatus register, the HC will start traversing through PTD headers that are not marked for skipping and are valid PTDs ...

  • Page 48

    ... NXP Semiconductors Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 43. Bit 8.3.7 ATL Done Timeout register The bit description of the ATL Done Timeout register is given in Table 44. ATL Done Timeout register (address 0338h) bit description ...

  • Page 49

    ... NXP Semiconductors Table 45. Memory register (address 033Ch) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...

  • Page 50

    ... NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 48. Bit 8.3.10 DMA Start Address register This register defines the start address select for the DMA read and write operations. See Table 49 Table 49 ...

  • Page 51

    ... NXP Semiconductors Table 50. Bit 8.3.11 Power Down Control register This register is used to turn off power to internal blocks of the ISP1761 to obtain maximum power savings. Table 51. Power Down Control register (address 0354h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset ...

  • Page 52

    ... NXP Semiconductors Table 52. [1] Bit ISP1761_4 Product data sheet Power Down Control register (address 0354h) bit description Symbol Description CLK_OFF_ Clock Off Counter: Determines the wake-up status duration after any COUNTER wake-up event before the ISP1761 goes back into suspend mode. ...

  • Page 53

    ... NXP Semiconductors Table 52. [1] Bit [1] For a 32-bit operation, the default wake-up counter value For a 16-bit operation, the wake-up counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization. 8.4 Interrupt registers 8.4.1 HcInterrupt register The bits of this register indicate the interrupt source, defining the events that determined the INT generation ...

  • Page 54

    ... NXP Semiconductors Bit 7 Symbol INT_IRQ CLK READY Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 54. Bit ISP1761_4 Product data sheet [1] HCSUSP reserved R/W R/W HcInterrupt - Host Controller Interrupt register (address 0310h) bit description Symbol Description reserved ...

  • Page 55

    ... NXP Semiconductors Table 54. Bit 8.4.2 HcInterruptEnable register This register allows enabling or disabling of the IRQ generation because of various events as described in Table 55. HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W ...

  • Page 56

    ... NXP Semiconductors Bit 7 Symbol INT_IRQ_E CLKREADY Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 56. Bit ISP1761_4 Product data sheet [1] HCSUSP_ reserved R/W R/W HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit description Symbol Description reserved ...

  • Page 57

    ... NXP Semiconductors Table 56. Bit 8.4.3 ISO IRQ MASK OR register Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done map. See see Section Table 57. ISO IRQ Mask OR register (address 0318h) bit description ...

  • Page 58

    ... NXP Semiconductors Table 59. ATL IRQ Mask OR register (address 0320h) bit description Bit Symbol Access Value ATL_IRQ_MASK_ R/W OR[31:0] 8.4.6 ISO IRQ MASK AND register Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Table 60 Table 60 ...

  • Page 59

    ... NXP Semiconductors The PTD structures of the ISP1761 are translations of EHCI data structures that are optimized for the ISP1761. It, however, still follows the basic EHCI architecture. This optimized form of EHCI data structures is necessary because the ISP1761 is a slave Host Controller and has no bus master capability. ...

  • Page 60

    ... NXP Semiconductors 5. If combined with skip, the skip must not be set (logically) on the same position corresponding to NextPTD, pointed by the NextPTD pointer PTD is set for skip, it will be neglected and the next vertical PTD will be considered the skipped PTD already has a setting including a NextPTD pointer that will not be taken into consideration, the behavior will be just as described in the preceding step ...

  • Page 61

    High-speed bulk IN and OUT Table 63 shows the bit allocation of the high-speed bulk IN and OUT, asynchronous Transfer Descriptor. Table 63. High-speed bulk IN and OUT: bit allocation Bit ...

  • Page 62

    ... NXP Semiconductors Table 64. High-speed bulk IN and OUT: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - — writes - NextPTDPointer SW — writes - [4:0] DW3 — sets HW — resets — writes - — writes - — writes - SW — writes - 59 reserved - — writes HW — ...

  • Page 63

    ... NXP Semiconductors Table 64. High-speed bulk IN and OUT: bit description Bit Symbol Access Cerr[1:0] HW — writes SW — writes NakCnt[3:0] HW — writes SW — writes reserved - NrBytes HW — writes Transferred SW — writes [14:0] 0000 DW2 reserved - RL[3:0] SW — writes - 24 reserved - DataStart SW — writes - Address[15:0] ...

  • Page 64

    ... NXP Semiconductors Table 64. High-speed bulk IN and OUT: bit description Bit Symbol Access Mult[1:0] SW — writes - MaxPacket SW — writes - Length[10: NrBytesTo SW — writes - Transfer[14: reserved - — sets HW — resets ISP1761_4 Product data sheet …continued Value Description Multiplier: This field is a multiplier used by the Host Controller as the number of successive packets the Host Controller may submit to the endpoint in the current execution ...

  • Page 65

    High-speed isochronous IN and OUT Table 65 shows the bit allocation of the high-speed isochronous IN and OUT, isochronous Transfer Descriptor (iTD). Table 65. High-speed isochronous IN and OUT: bit allocation Bit ...

  • Page 66

    ... NXP Semiconductors Table 66. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW7 ISOIN_7[11:0] HW — writes ISOIN_6[11:0] HW — writes ISOIN_5[11:4] HW — writes DW6 ISOIN_5[3:0] HW — writes ISOIN_4[11:0] HW — writes ISOIN_3[11:0] HW — writes ISOIN_2[11:8] HW — writes DW5 ISOIN_2[7:0] HW — writes ISOIN_1[11:0] HW — writes ISOIN_0[11:0] HW — ...

  • Page 67

    ... NXP Semiconductors Table 66. High-speed isochronous IN and OUT: bit description Bit Symbol Access — writes — writes reserved - NrBytes HW — writes Transferred [14:0] DW2 reserved - DataStart SW — writes Address[15: Frame[7:0] SW — writes DW1 reserved - — writes EPType[1:0] SW — writes Token[1:0] SW — writes ...

  • Page 68

    ... NXP Semiconductors Table 66. High-speed isochronous IN and OUT: bit description Bit Symbol Access NrBytesTo SW — writes Transfer[14: reserved - — resets SW — sets ISP1761_4 Product data sheet …continued Value Description - Number of Bytes Transferred: This field indicates the number of bytes that can be transferred by this data structure used to indicate the depth of the DATA fi ...

  • Page 69

    High-speed interrupt IN and OUT Table 67 shows the bit allocation of the high-speed interrupt IN and OUT, periodic Transfer Descriptor (pTD). Table 67. High-speed interrupt IN and OUT: bit allocation Bit ...

  • Page 70

    ... NXP Semiconductors Table 68. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW7 INT_IN_7[11:0] HW — writes INT_IN_6[11:0] HW — writes INT_IN_5[11:4] HW — writes DW6 INT_IN_5[3:0] HW — writes INT_IN_4[11:0] HW — writes INT_IN_3[11:0] HW — writes INT_IN_2[11:8] HW — writes DW5 INT_IN_2[7:0] HW — writes INT_IN_1[11:0] HW — writes INT_IN_0[11:0] HW — ...

  • Page 71

    ... NXP Semiconductors Table 68. High-speed interrupt IN and OUT: bit description Bit Symbol Access — writes reserved - — writes SW — writes Cerr[1:0] HW — writes SW — writes reserved - NrBytes HW — writes Transferred [14:0] DW2 reserved - DataStart SW — writes Address[15: Frame[7:0] SW — writes DW1 reserved ...

  • Page 72

    ... NXP Semiconductors Table 68. High-speed interrupt IN and OUT: bit description Bit Symbol Access MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets Table 69 ISP1761_4 Product data sheet …continued Value Description - Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet ...

  • Page 73

    Start and complete split for bulk Table 70 shows the bit allocation of Start Split (SS) and Complete Split (CS) for bulk, asynchronous Start Split and Complete Split (SS/CS) Transfer Descriptor. Table 70. Start and complete split for bulk: ...

  • Page 74

    ... NXP Semiconductors Table 71. Start and complete split for bulk: bit description Bit Symbol DW7 reserved DW6 reserved DW5 reserved DW4 reserved NextPTDPointer[4:0] SW — writes DW3 reserved Cerr[1: NakCnt[3: reserved NrBytes Transferred[14:0] ISP1761_4 Product data sheet Access Value Description - - - - - - - ...

  • Page 75

    ... NXP Semiconductors Table 71. Start and complete split for bulk: bit description Bit Symbol DW2 reserved RL[3:0] 24 reserved DataStartAddress [15: reserved DW1 HubAddress[6: PortNumber[6: SE[1:0] 47 reserved EPType[1: Token[1: DeviceAddress[6: EndPt[3:1] DW0 31 EndPt[ reserved MaximumPacket Length[10:0] ISP1761_4 Product data sheet …continued Access Value Description ...

  • Page 76

    ... NXP Semiconductors Table 71. Start and complete split for bulk: bit description Bit Symbol NrBytesTo Transfer[14: reserved 0 V Table 72. Bulk I/O I/O ISP1761_4 Product data sheet …continued Access Value Description SW — writes - Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure used to indicate the depth of the DATA fi ...

  • Page 77

    Start and complete split for isochronous Table 73 shows the bit allocation for start and complete split for isochronous, split isochronous Transfer Descriptor (siTD). Table 73. Start and complete split for isochronous: bit allocation Bit ...

  • Page 78

    ... NXP Semiconductors Table 74. Start and complete split for isochronous: bit description Bit Symbol Access DW7 reserved - ISO_IN_7[7:0] HW — writes DW6 ISO_IN_6[7:0] HW — writes ISO_IN_5[7:0] HW — writes ISO_IN_4[7:0] HW — writes ISO_IN_3[7:0] HW — writes DW5 ISO_IN_2[7:0] HW — writes ISO_IN_1[7:0] HW — writes ISO_IN_0[7:0] HW — writes ...

  • Page 79

    ... NXP Semiconductors Table 74. Start and complete split for isochronous: bit description Bit Symbol Access DW3 — sets HW — resets — writes — writes — writes — writes 0 HW — updates 58 reserved - — writes SW — writes reserved - NrBytes HW — writes Transferred [11:0] ...

  • Page 80

    ... NXP Semiconductors Table 74. Start and complete split for isochronous: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes reserved - TT_MPS_Len SW — writes [10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets ISP1761_4 Product data sheet …continued Value Description - Endpoint: This is the USB address of the endpoint within the function ...

  • Page 81

    Start and complete split for interrupt Table 75 shows the bit allocation of start and complete split for interrupt. Table 75. Start and complete split for interrupt: bit allocation Bit ...

  • Page 82

    ... NXP Semiconductors Table 76. Start and complete split for interrupt: bit description Bit Symbol Access DW7 reserved - INT_IN_7[7:0] HW — writes DW6 INT_IN_6[7:0] HW — writes INT_IN_5[7:0] HW — writes INT_IN_4[7:0] HW — writes INT_IN_3[7:0] HW — writes DW5 INT_IN_2[7:0] HW — writes INT_IN_1[7:0] HW — writes INT_IN_0[7:0] HW — writes ...

  • Page 83

    ... NXP Semiconductors Table 76. Start and complete split for interrupt: bit description Bit Symbol Access SA[7:0] SW — writes (0 HW — writes (1 After processing DW3 — sets HW — resets — writes — writes — writes — writes 0 HW — updates 58 reserved - — writes SW — ...

  • Page 84

    ... NXP Semiconductors Table 76. Start and complete split for interrupt: bit description Bit Symbol Access — writes EPType[1:0] SW — writes Token[1:0] SW — writes DeviceAddress SW — writes [6: EndPt[3:1] SW — writes DW0 31 EndPt[0] SW — writes reserved - MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14:0] ...

  • Page 85

    ... NXP Semiconductors 9. OTG Controller 9.1 Introduction OTG is a supplement to the Hi-Speed USB specification that augments existing USB peripherals by adding to these peripherals limited host capability to support other targeted USB peripherals primarily targeted at portable devices because it addresses concerns related to such devices, such as a small connector and low power. Non-portable devices, even standard hosts, can also benefi ...

  • Page 86

    ... NXP Semiconductors peripheral, and the A-device assumes the role of a host. The A-device detects that the B-device can support HNP by getting the OTG descriptor from the B-device. The A-device will then enable the HNP hand-off by using SetFeature (b_hnp_enable) and then go into the suspend state ...

  • Page 87

    ... NXP Semiconductors 9.4 Host Negotiation Protocol (HNP) HNP is used to transfer control of the host role between the default host (A-device) and the default peripheral (B-device) during a session. When the A-device is ready to give up its role as a host, it will condition the B-device using SetFeature (b_hnp_enable) and will go into suspend ...

  • Page 88

    ... NXP Semiconductors 6. The A-device detects lack of bus activity for more than 3 ms and turns off its DP pull-up. Alternatively, if the A-device has no further need to communicate with the B-device, the A-device may turn off V 7. The B-device turns on its pull-up. 8. After waiting ensure that the DP line is not HIGH because of the residual ...

  • Page 89

    ... NXP Semiconductors START id | a_bus_req | (a_sess_vld/ & b_conn/) a_wait_vfall drv_vbus/ loc_conn/ loc_sof a_bus_drop a_peripheral drv_vbus loc_conn loc_sof/ b_conn/ & a_set_b_hnp_en id | a_bus_drop | a_aidl_bdis_tmout a_suspend drv_vbus loc_conn/ loc_sof/ Fig 15. Dual-role A-device state diagram ISP1761_4 Product data sheet a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof a_bus_drop | a_wait_bcon_tmout ...

  • Page 90

    ... NXP Semiconductors START id/ | b_sess_vld/ b_host chrg_vbus/ loc_conn/ loc_sof a_conn b_wait_acon chrg_vbus/ loc_conn/ loc_sof/ Fig 16. Dual-role B-device state diagram 9.4.3 HNP implementation and OTG state machine The OTG state machine is the software behind all the OTG functionality implemented in the microprocessor system that is connected to the ISP1761. The ISP1761 provides ...

  • Page 91

    ... NXP Semiconductors 2. Set the corresponding bits of the OTG Interrupt Enable Rise and OTG Interrupt Enable Fall registers. 3. Set bit OTG_IRQ_E of the HcInterruptEnable register (bit 10). 4. Set bit GLOBAL_INTR_EN of the HW Mode Control register (bit 0). When an interrupt is generated on HC_IRQ, perform these steps in the interrupt service routine to get the related OTG status: 1 ...

  • Page 92

    ... OTG Timer (Lower word: clear) OTG Timer (Higher word: set) OTG Timer (Higher word: clear) shows the bit description of the register. Access Value Description R 04CCh NXP Semiconductors’ Vendor ID Access Value Description R 1761h Product ID of the ISP1761 Rev. 04 — 5 March 2007 ISP1761 Hi-Speed USB OTG controller … ...

  • Page 93

    ... NXP Semiconductors 9.5.2 OTG Control register 9.5.2.1 OTG Control register Table 84 Table 84. OTG Control register (address set: 0374h, clear: 0376h) bit allocation Bit 15 Symbol Reset 0 Access R/S/C R/S/C Bit 7 Symbol SW_SEL_ VBUS_ HC_DC CHRG Reset 1 Access R/S/C R/S/C [1] The reserved bits should always be written with the reset value. ...

  • Page 94

    ... NXP Semiconductors Table 85. [1] Bit [1] To use port Host Controller, write 0080 0018h to this register after power-on. To use port Peripheral Controller, write 0006 0400h to this register after power-on. 9.5.3 OTG Interrupt registers 9.5.3.1 OTG Status register This register indicates the current state of the signals that can generate an interrupt. The bit allocation of the register is given in Table 86 ...

  • Page 95

    ... NXP Semiconductors Table 87. Bit 9.5.3.2 OTG Interrupt Latch register The OTG Interrupt Latch register indicates the source that generated the interrupt. The status of this register bits depends on the settings of the Interrupt Enable Fall and Interrupt Enable Rise registers, and the occurrence of the respective events. ...

  • Page 96

    ... NXP Semiconductors 9.5.3.3 OTG Interrupt Enable Fall register Table 90 HIGH-to-LOW. Table 90. OTG Interrupt Enable Fall register (address set: 0380h, clear: 0382h) bit allocation Bit 15 Symbol Reset 0 Access R/S/C R/S/C Bit 7 Symbol B_SESS_ END Reset 0 Access R/S/C R/S/C [1] The reserved bits should always be written with the reset value. ...

  • Page 97

    ... NXP Semiconductors Bit 7 Symbol B_SESS_ BDIS_ END ACON Reset 0 Access R/S/C R/S/C [1] The reserved bits should always be written with the reset value. Table 93. Bit 9.5.4 OTG Timer register 9.5.4.1 OTG Timer register This is a 32-bit register organized as two 16-bit fields. These two fields have separate set and clear addresses ...

  • Page 98

    ... NXP Semiconductors Bit 7 Symbol Reset 0 Access R/S/C R/S/C [1] The reserved bits should always be written with the reset value. Table 95. Bit ISP1761_4 Product data sheet TIMER_INIT_VALUE[7: R/S/C R/S/C OTG Timer register (address low word set: 0388h, low word clear: 038Ah; high word set: 038Ch, high word clear: 038Eh) bit description ...

  • Page 99

    ... NXP Semiconductors 10. Peripheral Controller 10.1 Introduction The design of the Peripheral Controller in the ISP1761 is compatible with the NXP ISP1582 Hi-Speed Universal Serial Bus peripheral controller IC. The functionality of the Peripheral Controller in the ISP1761 is similar to the ISP1582 in 16-bit bus mode. In addition, the register sets are also similar, with only a few variations. ...

  • Page 100

    ... NXP Semiconductors Peripheral Controller. If DMA is not required by the application, DMACLKON can be permanently disabled to save current. The burst counter, DMA bus width, and the polarity of DC_DREQ and DC_DACK must accordingly be set. The ISP1761 supports only counter mode DMA transfer. To enable counter mode, ensure that DIS_XFER_CNT in the DcDMAConfi ...

  • Page 101

    ... NXP Semiconductors If bit DMA_XFER_OK in the DMA Interrupt Reason register is asserted, it means that the transfer counter has reached zero and the DMA transfer is successfully stopped. If bit INT_EOT in the DMA Interrupt Reason register is set, it indicates that a short or empty packet is received. This means that DMA transfer terminated. Normally, for an OUT transfer, it means that remote host wishes to terminate the DMA transfer ...

  • Page 102

    ... NXP Semiconductors Table 96. Endpoint identifier EP6RX EP6TX EP7RX EP7TX 10.3 Clear buffer Use clear buffer when data needs to be discarded under the following conditions: • IN endpoint: If the host aborts a read operation, the residual data in the IN endpoint buffer must be cleared using the Clear Buffer command. See • ...

  • Page 103

    ... NXP Semiconductors • In 32-bit bus access mode, the register addresses are 4 bytes aligned. Therefore, the DcBufferStatus register can be accessed using the upper-two bytes of the Buffer Length register. • The SOFTCT bit in the Mode register has been removed. The DP_PULLUP control bit in the OTG Control register is used in the ISP1761 in place of the SOFTCT bit in the ISP1582 ...

  • Page 104

    ... NXP Semiconductors Table 97. Address Register 0228h 0220h 021Ch 021Eh 0204h 0208h DMA registers 0230h 0234h 0238h 023Ch 0250h 0254h 0258h 0264h General registers 0218h 0270h 0274h 0278h 027Ch 0280h 0284h 10.5.1 Address register This register sets the USB assigned address and enables the USB peripheral. ...

  • Page 105

    ... NXP Semiconductors Table 99. Bit 10.5.2 Mode register This register consists of 2 bytes (bit allocation: see The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft reset and clock signals. Table 100. Mode register (address 020Ch) bit allocation Bit 15 Symbol ...

  • Page 106

    ... NXP Semiconductors Table 101. Mode register (address 020Ch) bit description Bit 10.5.3 Interrupt Configuration register This 1 byte register determines the behavior and polarity of the INT output. The bit allocation is shown in or NYET, it will generate interrupts depending on three Debug mode fields. ...

  • Page 107

    ... NXP Semiconductors Table 103. Interrupt Configuration register (address 0210h) bit description Bit Symbol CDBGMOD[1: DDBGMODIN[1: DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see 1 INTLVL 0 INTPOL Table 104. Debug mode settings Value 00h 01h 1Xh [1] First NAK: The first NAK OUT token after a previous ACK response. ...

  • Page 108

    ... NXP Semiconductors 10.5.5 DcInterruptEnable register This register enables or disables individual interrupt sources. The interrupt for each endpoint can individually be controlled through the associated IEPnRX or IEPnTX bits, here n represents the endpoint number. All interrupts can globally be disabled through bit GLINTENA in the Mode register (see An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the USB bus. The interrupt generation depends on Debug mode settings of bit fi ...

  • Page 109

    ... NXP Semiconductors Table 108. DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h) Bit 10.6 Data flow registers 10.6.1 Endpoint Index register The Endpoint Index register selects a target endpoint for register access by the microcontroller. The register consists of 1 byte, and the bit allocation is shown in Table 109 ...

  • Page 110

    ... NXP Semiconductors • Endpoint MaxPacketSize • Endpoint Type For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the Endpoint Index register must be written first with 02h. Remark: The Endpoint Index register and the DMA Endpoint register must not point to the same endpoint, irrespective of IN and OUT ...

  • Page 111

    ... NXP Semiconductors Table 112. Control Function register (address 0228h) bit allocation Bit 7 Symbol reserved Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 113. Control Function register (address 0228h) bit description Bit ISP1761_4 ...

  • Page 112

    ... NXP Semiconductors 10.6.3 Data Port register This register provides direct access for a microcontroller to the FIFO of the indexed endpoint. Peripheral to host (IN endpoint): After each write, an internal counter is automatically incremented, by two in 16-bit mode and four in 32-bit mode, to the next location in the TX FIFO. When all bytes have been written (FIFO byte count = endpoint MaxPacketSize), the buffer is automatically validated ...

  • Page 113

    ... NXP Semiconductors Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is programmed as 64 bytes, the Buffer Length register should be filled with 62 bytes just before the microcontroller writes the last packet of 62 bytes. This ensures that the last packet, which is a short packet of 62 bytes, is automatically validated. ...

  • Page 114

    ... NXP Semiconductors 10.6.6 Endpoint MaxPacketSize register This register determines the maximum packet size for all endpoints, except control 0. The register contains 2 bytes, and the bit allocation is given in Each time the register is written, the Buffer Length register of the corresponding endpoint is re-initialized to the FFOSZ field value. NTRANS bits control the number of transactions allowed in a single micro frame for high-speed isochronous and interrupt endpoints only ...

  • Page 115

    ... NXP Semiconductors Table 121. Endpoint Type register (address 0208h) bit allocation Bit 15 Symbol Reset 0 Bus reset 0 Access R/W R/W Bit 7 Symbol reserved Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 122. Endpoint Type register (address 0208h) bit description ...

  • Page 116

    ... NXP Semiconductors In counter mode, the DIS_XFER_CNT bit in the DcDMAConfiguration register must be set to logic 0. The DMA Transfer Counter register must be programmed before any DMA command is issued. The DMA transfer counter is set by writing from the LSByte to the MSByte (address: 234h to 237h). The DMA transfer count is internally updated only after the MSByte is written ...

  • Page 117

    ... NXP Semiconductors Table 125. DMA Command register (address 0230h) bit description Bit Table 126. DMA commands Code 00h 01h 02h to 0Dh - 0Eh 0Fh 10h 11h 12h 13h 14h to FFh - 10.7.2 DMA Transfer Counter register This 4 bytes register sets up the total byte count for a DMA transfer (DMACR). It indicates the remaining number of bytes left for transfer. The bit allocation is given in For IN endpoint — ...

  • Page 118

    ... NXP Semiconductors Table 127. DMA Transfer Counter register (address 0234h) bit allocation Bit 31 Symbol Reset 0 Bus reset 0 Access R/W Bit 23 Symbol Reset 0 Bus reset 0 Access R/W Bit 15 Symbol Reset 0 Bus reset 0 Access R/W Bit 7 Symbol Reset 0 Bus reset 0 Access R/W Table 128. DMA Transfer Counter register (address 0234h) bit description ...

  • Page 119

    ... NXP Semiconductors Bit 7 Symbol DIS_ XFER_CNT Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 130. DcDMAConfiguration - Device Controller Direct Memory Access Configuration Bit 10.7.4 DMA Hardware register The DMA Hardware register consists of 1 byte. The bit allocation is shown in This register determines the polarity of bus control signals (DACK and DREQ) ...

  • Page 120

    ... NXP Semiconductors Table 132. DMA Hardware register (address 023Ch) bit description Bit 10.7.5 DMA Interrupt Reason register This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a DMA command is executed. An interrupt source is cleared by writing logic 1 to the corresponding bit. On detecting the interrupt, the external microprocessor must read the DMA Interrupt Reason register and mask it with the corresponding bits in the DMA Interrupt Enable register to determine the source of the interrupt ...

  • Page 121

    ... NXP Semiconductors Table 134. DMA Interrupt Reason register (address 0250h) bit description Bit Table 135. Internal EOT-functional relation with the DMA_XFER_OK bit INT_EOT 10.7.6 DMA Interrupt Enable register This 2 bytes register controls the interrupt generation of the source bits in the DMA Interrupt Reason register. The bit allocation is given in given in Logic 1 enables the interrupt generation ...

  • Page 122

    ... NXP Semiconductors Table 137. DMA Endpoint register (address 0258h) bit allocation Bit 7 Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 138. DMA Endpoint register (address 0258h) bit description Bit The DMA Endpoint register must not reference the endpoint that is indexed by the Endpoint Index register (022Ch) at any time ...

  • Page 123

    ... NXP Semiconductors Table 140. DMA Burst Counter register (address 0264h) bit description Bit 10.8 General registers 10.8.1 DcInterrupt register The DcInterrupt register consists of 4 bytes. The bit allocation is given in When a bit is set in the DcInterrupt register, it indicates that the hardware condition for an interrupt has occurred ...

  • Page 124

    ... NXP Semiconductors Bit 7 Symbol VBUS DMA Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit Bit ISP1761_4 Product data sheet HS_STAT RESUME R/W R/W ...

  • Page 125

    ... NXP Semiconductors 10.8.2 DcChipID register This read-only register contains the chip identification and hardware version numbers. The firmware must check this information to determine functions and features supported. The register contains 3 bytes, and the bit allocation is shown in Table 143. DcChipID - Device Controller Chip Identifier register (address 0270h) bit description ...

  • Page 126

    ... NXP Semiconductors Bit 7 Symbol Reset 0 Bus reset Access R/W R/W Table 147. DcScratch - Device Controller Scratch register (address 0278h) bit description Bit 10.8.5 Unlock Device register To protect registers from getting corrupted when the ISP1761 goes into suspend, the write operation is disabled. In this case, when the chip resumes, the Unlock Device command must fi ...

  • Page 127

    ... NXP Semiconductors 10.8.7 Test Mode register This 1 byte register allows the firmware to set the DP and DM pins to predetermined states for testing purposes. The bit allocation is given in Remark: Only one bit can be set to logic time. Table 151. Test Mode register (address 0284h) bit allocation ...

  • Page 128

    ... NXP Semiconductors 11. Power consumption Table 153. Power consumption Number of ports working One port working (high-speed Two ports working (high-speed Three ports working (high-speed Remark: The idle operating current, I initialized and without any devices connected mA. The additional current consumption on I devices ...

  • Page 129

    ... NXP Semiconductors 12. Limiting values Table 154. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage CC(I/O) V supply voltage CC(5V0) V supply voltage CC(C_IN) I latch-up current lu V electrostatic discharge voltage esd T storage temperature stg 13. Recommended operating conditions Table 155 ...

  • Page 130

    ... NXP Semiconductors 14. Static characteristics Table 156. Static characteristics: digital pins [1] All digital pins , except pins ID, PSW1_N, PSW2_N, PSW3_N and BAT_ON_N +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) V HIGH-level input voltage IH V LOW-level input voltage IL V hysteresis voltage ...

  • Page 131

    ... NXP Semiconductors Table 158. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3 1. 3 +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter V high-speed idle level voltage HSOI V high-speed data signaling HSOH HIGH-level voltage V high-speed data signaling LOW-level HSOL ...

  • Page 132

    ... NXP Semiconductors Table 161. Static characteristics 1. 3 +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter R pull-up resistance on pin V UP(VBUS) R pull-down resistance on pin V DN(VBUS) R idle input resistance on pin V I(idle)(VBUS)(A) (A-device) R idle input resistance on pin V I(idle)(VBUS)(B) (B-device) Fig 17. Charge pump current versus voltage at various temperatures (worst case) Fig 18 ...

  • Page 133

    ... NXP Semiconductors 15. Dynamic characteristics Table 162. Dynamic characteristics: system clock timing +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Crystal oscillator f clock frequency clk External clock input J external clock jitter clock duty cycle V input voltage on pin XTAL1 i(XTAL1) t rise time ...

  • Page 134

    ... NXP Semiconductors Table 165. Dynamic characteristics: full-speed source electrical characteristics +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter t differential rise and fall time FRFM matching Z driver output impedance for DRV driver which is not high-speed capable Data timing: see Figure 19 ...

  • Page 135

    ... NXP Semiconductors 15.1 Host timing 15.1.1 PIO timing 15.1.1.1 Register or memory write Fig 20. Register or memory write Table 167. Register or memory write +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t h11 t h21 t h31 t w11 t su11 t su21 t su31 3.6 V CC(I/O) ...

  • Page 136

    ... NXP Semiconductors 15.1.1.2 Register read Fig 21. Register read Table 168. Register read +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t su12 t su22 t w12 t d12 t d22 3.6 V CC(I/O) t su12 t su22 t w12 t d12 t d22 15.1.1.3 Register access CS_N WR_N RD_N Fig 22 ...

  • Page 137

    ... NXP Semiconductors Table 169. Register access +85 C; unless otherwise specified. amb Symbol t WHRL t RHRL t RHWL t WHWL [1] For EHCI operational registers, minimum value is 195 ns. 15.1.1.4 Memory read A[17:1] DATA CS_N WR_N RD_N Fig 23. Memory read Table 170. Memory read +85 C; unless otherwise specified. ...

  • Page 138

    ... NXP Semiconductors Table 170. Memory read +85 C; unless otherwise specified. amb Symbol t w13 t su13 t su23 15.1.2 DMA timing In the following sections: • Polarity of DACK is active HIGH • Polarity of DREQ is active HIGH 15.1.2.1 Single cycle: DMA read Fig 24. DMA read (single cycle) Table 171 ...

  • Page 139

    ... NXP Semiconductors Table 171. DMA read (single cycle +85 C; unless otherwise specified. amb Symbol t a34 t a44 t h14 15.1.2.2 Single cycle: DMA write Fig 25. DMA write (single cycle) Table 172. DMA write (single cycle +85 C; unless otherwise specified. amb Symbol ...

  • Page 140

    ... NXP Semiconductors 15.1.2.3 Multi-cycle: DMA read Fig 26. DMA read (multi-cycle burst) Table 173. DMA read (multi-cycle burst +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t a16 t a26 t d16 t w16 T cy16 t a36 t a46 t h16 3.6 V CC(I/O) t a16 t a26 t d16 ...

  • Page 141

    ... NXP Semiconductors 15.1.2.4 Multi-cycle: DMA write Fig 27. DMA write (multi-cycle burst) Table 174. DMA write (multi-cycle burst +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) T cy17 t su17 t h17 t a17 t a27 t a37 t h27 t a47 t w17 t a57 3.6 V CC(I/O) ...

  • Page 142

    ... NXP Semiconductors 15.2 Peripheral timing 15.2.1 PIO timing 15.2.1.1 PIO register read or write CS_N AD[17:1] (read) DATA[31:0] RD_N (write) DATA[31:0] WR_N Fig 28. ISP1761 register access timing: separate address and data buses (8051 style) Table 175. PIO register read or write +85 C; unless otherwise specified. ...

  • Page 143

    ... NXP Semiconductors Table 175. PIO register read or write +85 C; unless otherwise specified. amb Symbol Parameter t d68 3.6 V CC(I/O) Reading t w18 t su18 t h18 t d18 t d28 t d38 t d48 Writing t w28 t su28 t h28 t su38 t h38 t d58 t d68 15.2.1.2 PIO register access CS_N ...

  • Page 144

    ... NXP Semiconductors 15.2.2 DMA timing 15.2.2.1 DMA read or write (2) DREQ t su19 (1) DACK t su39 RD_N/WR_N (read) DATA [ (write) DATA [ DREQ is continuously asserted until the last transfer is done or the FIFO is full. Data strobes: RD_N (read) and WR_N (write). (1) Programmable polarity: shown as active LOW. ...

  • Page 145

    ... NXP Semiconductors Table 177. DMA read or write +85 C; unless otherwise specified. amb Symbol Parameter t h19 t w19 t w29 t d29 t h29 t h39 t su29 t su39 t a19 ISP1761_4 Product data sheet …continued DREQ hold time after last strobe on RD_N/WR_N pulse width RD_N/WR_N recovery time ...

  • Page 146

    ... NXP Semiconductors 16. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 102 103 pin 1 index 128 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 147

    ... NXP Semiconductors TFBGA128: plastic thin fine-pitch ball grid array package; 128 balls; body 0.8 mm ball A1 index area ball index area 2 4 DIMENSIONS (mm are the original dimensions) A UNIT max 0.25 0.85 0.35 mm 1.1 0.15 0.75 0.25 OUTLINE VERSION IEC SOT857-1 Fig 32. Package outline SOT857-1 (TFBGA128) ...

  • Page 148

    ... NXP Semiconductors 17. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

  • Page 149

    ... NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

  • Page 150

    ... NXP Semiconductors Fig 33. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . ISP1761_4 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...

  • Page 151

    ... NXP Semiconductors 18. Abbreviations Table 180. Abbreviations Acronym ACK ASIC ATL ATX CS DMA DSC DW EHCI EMI EOP EOT ESD ESR FIFO FS FLS GDMA GPIO GPS HC HNP HS iTD INT ISO ISR ITL LS LSByte MSByte NAK NYET OC OHCI OTG PCI PID PIO ISP1761_4 Product data sheet ...

  • Page 152

    ... NXP Semiconductors Table 180. Abbreviations Acronym PLL PMOS POR PORP PTD RAM RISC SE0 SE1 SIE siTD SOF SRAM SRP SS TT UHCI USB 19. References [1] Universal Serial Bus Specification Rev. 2.0 [2] Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 [3] On-The-Go Supplement to the USB Specifi ...

  • Page 153

    ... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Changed OTG specification revision from 1.0a to 1.2. ...

  • Page 154

    ... NXP Semiconductors Table 181. Revision history …continued Document ID Release date • Modifications Table 52 “Power Down Control register (address 0354h) bit description”, Table 54 “HcInterrupt - (continued): Host Controller Interrupt register (address 0310h) bit description” and Table 56 “HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit description”: changed "reserved; write logic 0" ...

  • Page 155

    ... NXP Semiconductors Table 181. Revision history …continued Document ID Release date • Modifications Section 10.7.5 “DMA Interrupt Reason register”: updated the first paragraph. (continued): • Table 134 “DMA Interrupt Reason register (address 0250h) bit description”: updated bit 8 description. • ...

  • Page 156

    ... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

  • Page 157

    ... NXP Semiconductors 23. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 3. Port connection scenarios . . . . . . . . . . . . . . . .16 Table 4. Memory address . . . . . . . . . . . . . . . . . . . . . . .18 Table 5. Using the IRQ Mask AND or IRQ Mask OR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 6. Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 7. Pin status during hybrid mode . . . . . . . . . . . . .29 Table 8. Host Controller-specific register overview . . . .32 Table 9. ...

  • Page 158

    ... NXP Semiconductors bit description . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 49. DMA Start Address register (address 0344h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 50. DMA Start Address register (address 0344h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 51. Power Down Control register (address 0354h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 52. Power Down Control register (address 0354h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 53. HcInterrupt - Host Controller Interrupt register (address 0310h) bit allocation ...

  • Page 159

    ... NXP Semiconductors Table 100.Mode register (address 020Ch) bit allocation 105 Table 101.Mode register (address 020Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Table 102.Interrupt Configuration register (address 0210h) bit allocation . . . . . . . . . . . .106 Table 103.Interrupt Configuration register (address 0210h) bit description . . . . . . . . . . .107 Table 104.Debug mode settings . . . . . . . . . . . . . . . . . . .107 Table 105 ...

  • Page 160

    ... NXP Semiconductors Table 149.Unlock Device register (address 027Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Table 150.Interrupt Pulse Width register (address 0280h) bit description . . . . . . . . . . . . . . . . . .126 Table 151.Test Mode register (address 0284h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Table 152.Test Mode register (address 0284h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Table 153.Power consumption . . . . . . . . . . . . . . . . . . . .128 Table 154 ...

  • Page 161

    ... NXP Semiconductors 24. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 2. Pin configuration (LQFP128); top view . . . . . . . . .6 Fig 3. Pin configuration (TFBGA128); top view . . . . . . . .6 Fig 4. Internal hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Fig 5. ISP1761 clock scheme . . . . . . . . . . . . . . . . . . . .15 Fig 6. Memory segmentation and access block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Fig 7. ISP1761 power supply connection .27 Fig 8. Most commonly used power supply connection .28 Fig 9 ...

  • Page 162

    ... NXP Semiconductors 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 Host/peripheral roles Ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 14 7.1 ISP1761 internal architecture: advanced NXP slave Host Controller and hub 7.1.1 Internal clock scheme and port selection . . . . 15 7 ...

  • Page 163

    ... NXP Semiconductors 9.5.1.2 Product ID register (R: 0372h 9.5.2 OTG Control register . . . . . . . . . . . . . . . . . . . 93 9.5.2.1 OTG Control register . . . . . . . . . . . . . . . . . . . 93 9.5.3 OTG Interrupt registers 9.5.3.1 OTG Status register . . . . . . . . . . . . . . . . . . . . 94 9.5.3.2 OTG Interrupt Latch register 9.5.3.3 OTG Interrupt Enable Fall register . . . . . . . . . 96 9.5.3.4 OTG Interrupt Enable Rise register . . . . . . . . 96 9.5.4 OTG Timer register . . . . . . . . . . . . . . . . . . . . . 97 9 ...