ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 26

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
ISP1761_4
Product data sheet
7.7 Power supply
count, the ISP1761 will switch back to suspend mode after the specified time. The
maximum delay that can be programmed in the clock-off count field is approximately
500 ms.
Additionally, the Power Down Control register allows ISP1761 internal blocks to disable for
lower power consumption as defined in
The lowest suspend current, I
room temperature. The suspend current will increase with the increase in temperature,
with approximately 300 A at 40 C and up to a typical 1 mA at 85 C. The system is not in
suspend mode when its temperature increases above 40 C. Therefore, even a 1 mA
current consumption by the ISP1761 in suspend mode can be considered negligible. In
normal environmental conditions, when the system is in suspend mode, the maximum
ISP1761 temperature is approximately 40 C, determined by the ambient temperature.
Therefore, the ISP1761 maximum suspend current will be below 300 A. An alternative
solution to achieve a very low suspend current is to completely switch off the V
power input by using an external PMOS transistor, controlled by one of the GPIO pins of
the processor. This is possible because the ISP1761 can be used in hybrid mode, which
allows only the V
When the ISP1761 power is always on, the time from wake-up to suspend will be
approximately 100 ms.
It is necessary to wait for the CLKREADY interrupt assertion before programming the
ISP1761 because internal clocks are stopped during deep sleep suspend and restarted
after the first wake-up event. The occurrence of the CLKREADY interrupt means that
internal clocks are running and the normal functionality is achieved.
It is estimated that the CLKREADY interrupt will be generated less than 100 s after the
wake-up event, if the power to the ISP1761 was on during suspend.
If the ISP1761 is used in hybrid mode and V
pulse is required when the power is switched back on, before the resume programming
sequence starts. This will ensure that the internal clocks are running and all logics reach a
stable initial state.
Figure 7
shows the ISP1761 power supply connection.
CC(I/O)
Rev. 04 — 5 March 2007
powered on to avoid loading of the system bus.
CC(susp)
, that can be achieved is approximately 150 A at
Section
CC(5V0)
8.3.11.
is off during suspend, a 2 ms reset
Hi-Speed USB OTG controller
© NXP B.V. 2007. All rights reserved.
ISP1761
CC(5V0)
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