ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 16

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 3.
ISP1761_4
Product data sheet
Port configuration
One port (port 1)
One port (port 2)
One port (port 3)
Two ports (ports 1
and 2)
Two ports (ports 2
and 3)
Two ports (ports 1
and 3)
Three ports (ports 1,
2 and 3)
Port connection scenarios
7.2.1 General considerations
7.2 Host Controller buffer memory block
Port 1
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
Port 2 does not need to be enabled using software if only port 1 or port 3 is used. No port
needs to be disabled by external pull-up resistors, if not used. The DP and DM of the
unused ports need not be externally pulled HIGH because there are internal pull-down
resistors on each port that are enabled by default.
Table 3
The internal addressable Host Controller buffer memory is 63 kB. The 63 kB effective
memory size is the result of subtracting the size of the registers (1 kB) from the total
addressable memory space defined by the ISP1761 (64 kB). This is an optimized value to
achieve the highest performance with minimal cost.
The ISP1761 is a slave Host Controller. This means that it does not need access to the
local bus of the system to transfer data from the system memory to the ISP1761 internal
memory, unlike the case of the original PCI Hi-Speed USB Host Controllers. Therefore,
correct data must be transferred to both the Philips Transfer Descriptor (PTD) area and
the payload area by PIO (using CPU access) or programmed DMA.
The ‘slave-host’ architecture ensures better compatibility with most of the processors
present in the market today because not all processors allow a ‘bus-master’ on the local
bus. It also allows better load balancing of the processor’s local bus because only the
internal bus arbiter of the processor controls the transfer of data dedicated to USB. This
prevents the local bus from being busy when other more important transfers may be in the
queue; and therefore achieving a ‘linear’ system data flow that has less impact on other
processes running at the same time.
The considerations mentioned are also the main reason for implementing the pre-fetching
technique, instead of using a READY signal. The resulting architecture avoids ‘freezing’ of
the local bus, by asserting READY, enhancing the ISP1761 memory access time, and
avoiding introduction of programmed additional wait states. For details, see
lists the various port connection scenarios.
Rev. 04 — 5 March 2007
Port 2
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
Hi-Speed USB OTG controller
Port 3
DP and DM are not connected
(left open)
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
© NXP B.V. 2007. All rights reserved.
ISP1761
Section
16 of 163
7.3.