ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 102

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.11.3
12.11.4
102
ATtiny20
TCCR1C – Timer/Counter1 Control Register C
TCNT1H and TCNT1L – Timer/Counter1
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x[1:0] bits setting. Note that the
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x[1:0] bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bits 5:0 – Res: Reserved Bit
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be set to zero when the register is written.
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
Registers” on page
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-
pare match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
Bit
0x22
Read/Write
Initial Value
Bit
0x21
0x20
Read/Write
Initial Value
FOC1A
R/W
W
7
0
7
0
95.
FOC1B
R/W
W
6
0
6
0
R/W
R
5
–
0
5
0
R/W
R
4
–
0
4
0
TCNT1[15:8]
TCNT1[7:0]
R/W
R
3
0
3
–
0
R/W
2
0
R
2
–
0
R/W
1
0
–
R
1
0
“Accessing 16-bit
R/W
R
0
0
0
–
0
8235B–AVR–04/11
TCCR1C
TCNT1H
TCNT1L