ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 144

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.3.10
17.4
144
TWI Slave Operation
ATtiny20
Compatibility with SMBus
Figure 17-10. Clock Synchronization
A high to low transition on the SCL line will force the line low for all masters on the bus and they
start timing their low clock period. The timing length of the low clock period can vary between the
masters. When a master (DEVICE1 in this case) has completed its low period it releases the
SCL line. However, the SCL line will not go high before all masters have released it. Conse-
quently the SCL line will be held low by the device with the longest low period (DEVICE2).
Devices with shorter low periods must insert a wait-state until the clock is released. All masters
start their high period when the SCL line is released by all devices and has become high. The
device which first completes its high period (DEVICE1) forces the clock line low and the proce-
dure are then repeated. The result of this is that the device with the shortest clock period
determines the high period while the low period of the clock is determined by the longest clock
period.
As with any other I
should be aware of before connecting a TWI device to SMBus devices. For use in SMBus envi-
ronments, the following should be noted:
The TWI slave is byte-oriented with optional interrupts after each byte. There are separate inter-
rupt flags for Data Interrupt and Address/Stop Interrupt. Interrupt flags can be set to trigger the
• All I/O pins of an AVR, including those of the two-wire interface, have protection diodes to
• The data hold time of the TWI is lower than specified for SMBus. The TWSHE bit of
• SMBus has a low speed limit, while I
both supply voltage and ground. See
requirements of the SMBus specifications. As a result, supply voltage mustn’t be removed
from the AVR or the protection diodes will pull the bus lines down. Power down and sleep
modes is not a problem, provided supply voltages remain.
TWSCRA can be used to increase the hold time. See
Register A” on page
AVR must make sure bus speed does not drop below specifications, since lower bus speeds
trigger timeouts in SMBus slaves. If the AVR is configured a slave there is a possibility of a
bus lockup, since the TWI module doesn't identify timeouts.
2
C-compliant interface there are known compatibility issues the designer
146.
2
Figure 10-1 on page
C hasn’t. As a master in an SMBus environment, the
“TWSCRA – TWI Slave Control
44. This is in contradiction to the
8235B–AVR–04/11