ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 168

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

19.4.2
19.4.3
19.4.3.1
168
ATtiny20
Reading the Flash
Programming the Flash
Chip Erase
The most significant bits of the data space address select the NVM Lock bits or the Flash sec-
tion mapped to the data memory. The word address within a page (WADDR) is held by the bits
[WADDRMSB:1], and the page address (PADDR) is held by the bits [PADDRMSB:WAD-
DRMSB+1]. Together, PADDR and WADDR form the absolute address of a word in the Flash
section.
The least significant bit of the Flash section address is used to select the low or high byte of the
word.
The Flash can be read from the data memory mapped locations one byte at a time. For read
operations, the least significant bit (bit 0) is used to select the low or high byte in the word
address. If this bit is zero, the low byte is read, and if it is one, the high byte is read.
The Flash can be written two words at a time. Before writing a Flash double word, the Flash tar-
get location must be erased. Writing to an un-erased Flash word will corrupt its content.
The Flash is written two words at a time but the data space uses byte-addressing to access
Flash that has been mapped to data memory. It is therefore important to write the two words in
the correct order to the Flash, namely low bytes before high bytes. The low byte of the first word
is first written to the temporary buffer, then the high byte. Writing the low byte and then the high
byte to the buffer latches the two words into the Flash write buffer, starting the actual Flash write
operation.
The Flash erase operations can only performed for the entire Flash sections.
The Flash programming sequence is as follows:
The Chip Erase command will erase the entire code section of the Flash memory and the NVM
Lock Bits. For security reasons, however, the NVM Lock Bits are not reset before the code sec-
tion has been completely erased. The Configuration, Signature and Calibration sections are not
changed.
Before starting the Chip erase, the NVMCMD register must be loaded with the CHIP_ERASE
command. To start the erase operation a dummy byte must be written into the high byte of a
word location that resides inside the Flash code section. The NVMBSY bit remains set until eras-
ing has been completed. While the Flash is being erased neither Flash buffer loading nor Flash
reading can be performed.
The Chip Erase can be carried out as follows:
1. Perform a Flash section erase or perform a Chip erase
2. Write the Flash section two words at a time
1. Write the CHIP_ERASE command to the NVMCMD register
2. Start the erase operation by writing a dummy byte to the high byte of any word location
3. Wait until the NVMBSY bit has been cleared
inside the code section
8235B–AVR–04/11