ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 30

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8. System Control and Reset
8.1
8.2
8.2.1
30
Resetting the AVR
Reset Sources
ATtiny20
Power-on Reset
During reset, all I/O registers are set to their initial values, and the program starts execution from
the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump –
instruction to the reset handling routine. If the program never enables an interrupt source, the
interrupt vectors are not used, and regular program code can be placed at these locations. The
circuit diagram in
defined in section
Figure 8-1.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The start up
sequence is described in
The ATtiny20 has four sources of reset:
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level
is defined in section
whenever V
Reset, as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
• Brown Out Reset. The MCU is reset when the Brown-Out Detector is enabled and supply
RESET
RESET
threshold (V
than the minimum pulse length
Watchdog is enabled
voltage is below the brown-out threshold (V
V
CC
CC
CC
PULL-UP
PULL-UP
RESISTOR
RESISTOR
Reset Logic
is below the detection level. The POR circuit can be used to trigger the Start-up
POT
Figure 8-1
“System and Reset Characteristics” on page
)
FILTER
FILTER
SPIKE
SPIKE
“System and Reset Characteristics” on page
RSTDISBL
RSTDISBL
“Starting from Reset” on page
shows the reset logic. Electrical parameters of the reset circuitry are
DATA BUS
RESET CIRCUIT
RESET CIRCUIT
RESET CIRCUIT
RESET CIRCUIT
RESET CIRCUIT
RESET CIRCUIT
BODLEVEL2...0
BODLEVEL2...0
BROWN OUT
BROWN OUT
POWER-ON
POWER-ON
EXTERNAL
EXTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
WATCHDOG
WATCHDOG
WATCHDOG
RESET FLAG REGISTER
RESET FLAG REGISTER
TIMER
TIMER
BOT
(RSTFLR)
(RSTFLR)
)
20.
GENERATOR
GENERATOR
175.
CLOCK
CLOCK
COUNTER RESET
COUNTER RESET
CK
CK
175. The POR is activated
COUNTERS
COUNTERS
DELAY
DELAY
TIMEOUT
TIMEOUT
S
R
Q
8235B–AVR–04/11
INTERNAL
INTERNAL
RESET
RESET