ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 151

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5.6
8235B–AVR–04/11
TWSAM – TWI Slave Address Mask Register
When a master reads data from a slave, the data to be sent must be written to the TWSD regis-
ter. The byte transfer is started when the master starts to clock the data byte from the slave. It is
followed by the slave receiving the acknowledge bit from the master. The TWDIF and the TWCH
bits are then set.
When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte
has been received in the data register. If Smart Mode is enabled, reading the data register will
trigger the bus operation, as set by the TWAA bit in TWSCRB. Accessing TWSD in Smart Mode
will clear the slave data interrupt flag and the TWCH bit.
• Bits 7:1 – TWSAM[7:1]: TWI Address Mask
These bits can act as a second address match register, or an address mask register, depending
on the TWAE setting.
If TWAE is set to zero, TWSAM can be loaded with a 7-bit slave address mask. Each bit in
TWSAM can mask (disable) the corresponding address bit in the TWSA register. If the mask bit
is one the address match between the incoming address bit and the corresponding bit in TWSA
is ignored. In other words, masked bits will always match.
If TWAE is set to one, TWSAM can be loaded with a second slave address in addition to the
TWSA register. In this mode, the slave will match on 2 unique addresses, one in TWSA and the
other in TWSAM.
• Bit 0 – TWAE: TWI Address Enable
By default, this bit is zero and the TWSAM bits acts as an address mask to the TWSA register. If
this bit is set to one, the slave address match logic responds to the two unique addresses in
TWSA and TWSAM.
Bit
0x29
Read/Write
Initial Value
R/W
7
0
R/W
6
0
R/W
5
0
TWSAM[7:1]
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
TWAE
ATtiny20
R/W
0
0
TWSAM
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